Design Of CP-PLL Frequency Synthesizers

Wireless communication technology and Microelectronics technology has been booming for over a decade. The research in CMOS radio frequency (RF) communication system is tremendous. The PLL frequency synthesizer plays the most important roll in modern communication and message processing and is a key component in RF front. The design of fully integrated, fast lock-in PLL frequency synthesizers with low noise/spurs is an ever-lasting challenge in modern wireless communication systems. Among all kinds of circuits of PLL, CP-PLL has the advantages of fast frequency detector, acquisition wide frequency region, zero locked phase error, high speed, low power, and is the popular way of realizing PLL now.This paper describes the operating theory of CP-PLL synthesizer, and puts the ways of improving it on the basis of analyzing high noise and high jitter to realize the stable output of frequency, less lock-in time and better phase noise. And this paper designs high accuracy current mirror as current mode VCO to provide the stable current, realize high linearity of VCO gain which has few changes by the change of temperature and voltage and satisfy the need of stable frequency of PLL. In addition, this paper analyzes the reason of mismatch and puts the effective way to solve it.