The Design Of480MHz Phase Locked Loop For USB2.0

Now human has entered a multimedia ear when information is carried in the form of audio and video, and the volume of information is exploding, a highly efficient data transporting interface becomes a hot spot for both market and research. USB2.0interface standard is widly used in people’s life because it can increase the date rate up to480Mbps between two equipments. There are three types of USB2.0products on the market today:High speed, Full-speed and Low-speed, which the theoretical communication speed of high-speed mode is480Mbps.The phase-locked loop is the key module of USB2.0system because it provides clock of the system, it directly affects the performance and function of USB2.0system.Through the using of self-biased techniques in this paper, it will increase the PLL output frequency range and improve the performance of PLL phase noise.The main work of this paper is providing the whole design proposal for the self-basid PLL.The specific work of this paper can be summarized as follows:(1) Analyzing the operating principle, loop characteristic, noise feature and non-ideal behavior of PLL at the first. Introducing the operating principle and circuit of phase locked loop modules in detail:including charge pump, phase frequency detector, VCO, loop filter, dividers and so on.It is the reference and foundation for further research.(2) A self-biased PLL was designed and implemented in TSMC0.13μm CMOS technology, this PLL used self-biased technology. The phase-locked loop improve the phase noise performance of the output signal quality by using symmetric load, high linearity low noise charge pump, no dead zone phase frequency detector and other modules.(3) On the basis of theoretical analysis and systeml design theory, This PLL circuit was taped out by TSMC0.13um CMOS crafts. The final phase locked loop circuit chip core area is540um x280um=0.15mm2.Test results indicated that the PLL circuit operating at the frequency range from200MHz to800MHz,the center of the output frequency is480MHz, the phase noise of the phase-locked loops is-102dBc@1MHz at480MHz output frequency, the locking time is3.2μs, and the power consumption of the PLL is2mW when1.2V power supply.The preliminary test results show that the PLL designed by this parper achieves the desired function and performance index.