Research On Key Techniques Of High-resolution Noise Shaping Successive Approximation(NS-SAR) ADCs

In recent years,the Internet of things technology has gradually matured,driving the rapid development of integrated circuit industry.As the core of the Internet of Things technology,the chip has become a market seized by major companies.As a key module in the intermediate link of signal processing,ADC is an indispensable important circuit in all kinds of systems.In Io T applications,low power consumption and high precision requirements are proposed for ADCs.As a representative of low power ADC,SAR ADC is expected to have a large share in the Io T markets.However,the SAR ADC is limited in medium precision applications due to the thermal noise and offset of the comparator.Sigma-Delta ADC has its own advantages of high precision,but with advanced process,it makes more difficult to design of high performance operational amplifiers,which limits the design of Sigma-Delta ADC.Based on the characteristics of the two types of ADCs,the new architecture of noise shaping successive approximation ADC(NS SAR ADC)is proposed.NS SAR ADC has the characteristics of low power consumption,and at the same time,has the advantage of high resolution.In this thesis,the operational principle and two type's architecture of the NS SAR ADC are introduced.A simulink model of the 2^nd order based on a cascade IIR-FIR filter NS SAR ADC is presented,which can achieve both zero optimization and pole optimization.Thus,effectively improving the noise shaping efficiency.The IIR filter is mainly composed of the P-feedback loop and the Ping-Pong integrator.The P-feedback loop proposed in this thesis can achieve the 2^nd integration on the basis of the 1^st integration,which can reduce one input pair of comparators,effectively reduce the thermal noise,offset and kick-back noise of the comparator.In order to compensate for the integral loss and signal loss in the P-feedback loop,the Ping-Pong integrator based on the dynamic operational amplifier is proposed.The Ping-Pong integrator can make full use of the gain of the dynamic operational amplifier and effectively compensate for the integral loss and signal loss,thus realizing lossless integration.At the same time,the power consumption of dynamic operational amplifier is very low,which can realize the power efficiency of the system.To enhance the stability and noise shaping efficiency of the system,the FIR filter is added.Therefore,the pole of the noise transfer function(NTF)is moved from the right half plane to the left half plane.The FIR filter is only composed of some delay units,which can effectively reduce the power consumption of the system.A 100 MS/s NS SAR ADC is designed to verify the performance of the structure with the TSMC 65 nm 1.2 V process.An 8-bit SAR ADC is adopted as the quantizer,it adopts the V_CM-Based switch scheme to reduce the effect of charge injection and keep the common mode level unchanged.Meanwhile,redundant bit calibration technique is adopted to tolerate the incomplete settling of the CDAC,further to prevent the overload caused by feed-forward charge injection at the comparator input.Thus,extending the process of the residual signals processing.With the sampling frequency of 100 MS/s,the oversampling rate of 8,and the input signal frequency of 0.73 MHz.The post layout simulation shows that the ADC achieves the 94.3 d B SFDR and 87.6 d B SNDR.Compared with the conventional 8-bit SAR ADC,the proposed NS SAR achieves nearly 30 d B SNDR enhancements,which proves this design is suitable for the application of the high resolution and low power consumption Io T system.