Research On High-Order Noie-Shaping Successive Approximation Register Analog-to-Digital Converter

As the interface between analog system and digital system,analog-to-digital converter(ADC)is an important part of electronic system.With the rapid development of Internet-of-Things and wireless communication,the traditional ADC architecture can no longer meet the demand.The Internet-of-Things requires energy-efficient ADC with high resolution.The successive approximation analog-to-digital converter(SAR ADC)is a high-efficiency architecture,but the noise of the comparator and the capacitive array that increases exponentially with the increase in the number of bits limit the improvement of the resolution of the SAR ADC.The Delta-Sigma ADC can achieve high resolution,but the loop-filter based on operational amplifier(OTA)has high power consumption and undermines the scaling compatibility.The noise shaping(NS)SAR ADC combines the NS capability of the Delta-Sigma ADC with SAR ADCs to overcome the limitations of SAR ADCs by shaping the quantization noise and compaprator nosie,which can achieve high resolution and high energy efficiency simultaneously.The wireless communication calls for high-resolution,high-power-efficiency and high-dynamic-range ADC with tens of mega-hertz bandwidth.Traditional continuous-time Delta-Sigma ADCs experience the signal transfer function peaking issue.Furthermore,the necessary power-hungry OTA in the loop-filter confines the energy efficiency.Restricted by the serial conversion mechanism and NS operation,NS SAR ADCs hardly achieve the target bandwidth while preserve high resolution.The pipeline architecture can achieve parallel operation,increasing the conversion speed;therefore,the use of the pipeline architecture in the NS SAR ADC can achieve high-speed conversion,while preserving high energy efficiency and high precision.It is the latest research interest in low-power,high-speed and high-precision ADCs.This dissertation studies the system architecture and design method of high-order NS SAR ADCs.This dissertation firstly studies the accuracy improvement techniques of SAR ADCs at the circuit level and system level.The main noise sources in SAR ADCs are analyzed,and low-noise circuit implementation are studied.Then,the principle of NS is explained in time domain and frequency domain.Finally,the basic structure and working principle of two types of NS SAR ADCs,which are feed-forward(FF)and error feedback(EF),are studied.Based on the 65nm technology,under FF structure,a standard 2nd-order NS SAR ADC is proposed.In order to fully compensate the signal loss and integration loss caused by passive integration,a structure combining a Ping-pong switch-capacitor structure and a low-gain dynamic amplifier is proposed to achieve lossless integration.Based on the lossless integrator,the NS SAR ADC can achieve standard 2^nd-order NS,which improves the efficiency of NS.For the same quantization noise budget,the standard NS allows a larger residue,which reduces the resolution of the DAC and the requirements for comparator noise.The ADC achieves both high resolution and high energy-efficiency,which is suitable for Io Ts that requires low design complexity.At the supply voltage of 1.2V,the ADC consumes1.24mW at 100 MS/s resulting in the Fo MS of 171dB.At the OSR of 16,the bandwidth is3.125MHz.At 0.38MHz input,the SNDR is 77dB and the SFDR is 90.1dB.The DR is 78.2dB.Based on the 28nm technology,under EF structure,a 2nd-order zero-optimized NS Pipelined-SAR ADC is proposed.The partial-interleaving structure and coarse SAR ADC are introduced in the 1st stage to prolong the sampling time and speed up the conversion,simultaneously.Furthermore,the dynamic amplifier is adopted as the residue amplifier to enhance power efficiency.With an extra input pair in the dynamic amplifier,it servers both for residue amplification and feedback for EF residue summation,thus realizing the 2nd-order zero-optimazed NS in the 2nd-stage ADC.The prototype also includes a split-over-time facilitated gain calibration with a convergence enhancement configuration,realizing a fast background calibration.The inter-stage offset is calibrated at the background based on the split-ADC structure,avoiding the additional hardware overhead.It has the advantages of fast convergence and low power consumption.At the supply voltage of 1V,the ADC consumes 3.1mW at 260MS/s resulting in the Fo MS of 177.2dB.At the OSR of 6.5,the bandwidth is 20MHz.At 3.5-MHz input,the SNDR is 79.1dB and the SFDR is 90.4dB.The DR is 80.8dB.Compared with ADCs,the bandwidth is extended by 4-fold from previous designs with similar SNDR performance...