Research And Design Of An High-precision Adc For Image Sensor

CMOS image sensors have a wide range of applications in the Internet of Things,security detection and other fields.Achieving high frame rates and high resolutions on the premise of low cost is a research hotspot that the industry is currently paying close attention to.As the core module of CMOS image sensor,analog-to-digital converter(ADC)is the main factor that restricts the performance of image sensor in all aspects.Combining the medium-speed low-power features of successive approximation(SAR)ADCs with the high-accuracy features of Sigma-Delta ADCs,noise-shaping SAR ADCs can achieve medium-speed and high-precision with lower power consumption,which is beneficial to improving the performance of image sensors.Based on a 130 nm CMOS process,this article designs a 1MS / s noise-shaping SAR ADC with a 1.2V power supply,an oversampling rate of 8 and a capacitor DAC bit number of 8.Firstly,this paper analyzes the structural principles and advantages and disadvantages of two noise-shaping SAR ADCs.From this,a noise-shaping SAR structure is selected.Based on the principle analysis of the residual sampling capacitor and the residual operational amplifier to amplify the feedback residual,a new type of SAR ADC is proposed.The second-order noise-shaping SAR ADC structure based on error feedback improves the feedback speed and accuracy of the system.Secondly,the influence of unit capacitor mismatch on noise shaping SAR ADC is analyzed,and it is found that its mismatch error does not participate in shaping in the shaping system,which affects the accuracy of the system.By introducing data weighted averaging technology(DWA),the first order of mismatch error Shaping,which reduces the ADC's requirements for capacitor accuracy,reduces the capacitor size,achieves a higher quantization speed,and achieves both accuracy and speed;focuses on the analysis of each noise component introduced in the noise shaping system and its generation.Factors and transmission characteristics,including the equivalent input noise of the comparator,the system quantization noise,the switching thermal noise,and the equivalent input noise of the op amp,etc.,as well as the impact of other non-ideal factors on the performance,determine the system tolerance range of each non-ideal factor,The system modeling and simulation verification of the noise-shaping SAR ADC proposed in this paper are performed by Matlab.Thirdly,each module of the noise-shaping SAR ADC studied in this paper is designed and simulated.Extending the amplification time of the operational amplifier to half a sampling period,alleviating the bandwidth pressure of the residual op amp and increasing the speed of the ADC;incorporating comparator noise into the noise shaping process,reducing the accuracy requirement and power consumption of the comparator;The DWA technology digitally improves the matching of the capacitor array;the lastposition capacitor dithering(Dither)technology is used to realize the random selection of capacitors and improve the ADC's spurious-free dynamic range(SFDR).Finally,the layout of the noise-shaping SAR ADC was designed in a 130 nm standard CMOS process,and simulation was performed after referencing.Simulation results show that at a sampling frequency of 1MS / s,the signal frequency is 61.58 KHz,the SFDR of the ADC is 97.34 dB,the signal-to-noise and distortion ratio SNDR is 76.96 dB,and the effective number of bits ENOB is 12.49 Bit.