Research and design of low jitter, wide locking-range all-digital phase-locked and delay-locked loops

PHASE-LOCKED loops (PLLs) and delay-locked loops (DLLs) are often used in integrated circuits in order to compensate for clock distribution delays and to improve overall system timing. PLLs are also widely used in clock recovery and frequency synthesis. When compared to traditional implementations of PLLs and DLLs, an all-digital approach will be found more suitable for monolithic implementation on the same die with other digital circuits. A robust, process-independent performance is expected using all digital techniques.; In this dissertation, several aspects of phase-locked and delay-locked loops are investigated, including building blocks, loop dynamics, noise and jitter. General design criteria are summarized for the all-digital implementation with the comparison to the traditional approaches and popular charge-pump analog implementation.; An all-digital phase-locked loop (ADPLL) using a proposed register-controlled oscillator (RCO) and all-digital phase frequency detector (PFD) is developed and fabricated using 0.18um CMOS technology. The two-loop architecture, hierarchy pull-in process and fine phase adjustment make this RCO-based ADPLL achieve less than 80-cycle lock time, 65MHz–385MHz lock range, 30ps RMS jitter and less than 2% duty cycle distortion when the reference clock is at 200MHz. This ADPLL also shows stable operation when power supply voltage is down to 1.4V, which gives more flexibility in low power applications without significant design modification.; A register-controlled symmetrical DLL (RSDLL), targeted for clock synchronization and de-skewing in double-data rate synchronous DRAM, is implemented based on a symmetrical register-controlled delay line. This RSDLL was fabricated using 0.21 μm CMOS technology and achieved 50ps RMS jitter when the operating frequency is in the range of 125MHz to 250MHz. This approach eliminates extra circuitry for duty cycle correction when using both rising and falling edges to latch data. Measurement results are presented to verify its robust operation under different voltage and temperature conditions.