Study And Design Of Multiplying Delay-locked Loop

Phase-locking techniques are widely used in wireless transceivers,transmission interfaces,microprocessors and other fields.The design of a series of circuits,including Phase-Locked Loop(PLL),SerDes,Clock and Data Recovery(CDR)circuit,has been the focus of research in universities,research institutes and enterprises all over the world.In recent years,with the rapid development of the Internet of Things(IoT)technology and semiconductor technology,microprocessors are becoming more and more powerful.Data exchange between digital equipments is getting faster and faster.How to improve the speed while ensuring the reliability of data transmission is a topic worthy of study.In many applications,the high-speed serial interfaces have gradually replaced traditional parallel interfaces.PLLs are often used to generate high-frequency clock signals in high-speed serial interfaces.However.the jitter accumulation problem of the PLL itself increases the jitter on the output clock,which will limit the speed of data transmission.In general,a Delay-Locked Loop(DLL)has lower jitter than a PLL.So,in some applications requiring higher clock jitter performance,DLLs are preferred.But,because they can not achieve the function of frequency multiplication flexibly as PLLs do,its application has been limited.In this thesis,based on the analysis and comparison of two kinds of common-used phase-locking circuits,PLL and DLL.Multiplying Delay-Locked Loop(MDLL),a new phase-locking technique that combines the advantages of PLL and DLL is introduced.It overcomes the problem of jitter accumulation in traditional PLL while maintaining the advantage of a PLL for flexible frequency multiplication.Then,the principle and structure of a MDLL circuit are analyzed in detail.The design of the whole circuit from schematic to layout with 0.18 ?m standard CMOS process is presented.The frequency multiplication ratio of the MDLL is 7.The frequency of the reference that can be captured ranges from 25 MHz to 100 MHz.At the end of this thesis,the simulation results are shown.They indicate that when the process parameters,power supply voltage and temperature change in a certain range,the MDLL can always operate stably.When a 100 MHz reference is fed to the loop,the output clock has a frequency of 700 MHz and has a jitter less than 26 ps(peak to peak).