Design And Research On Multi-phase Digital Delay Locked Loop

The clock signal is a key signal for the digital circuits. Its delay and phase shift caused by the transfer process between two different modules are considered as two important indicators which can determine whether the distribution quality of a clock is good or not. With the function of the integrated circuit chip is becoming more perfect, is developing towards the direction named SoC, which means System on a chip, the area of the chip is also getting larger and larger. However, the delay of the interconnection wires often leads to the accumulation of the signal delay, which will cause serious timing errors, and even lead to dysfunction.In order to eliminate the clock delay among the different modules on a chip and reduce the phase shift of the clock, a low-power, easy to achieve Digital delay locked loop is designed in this paper. This kind of DLL's base construction is made up of the delay units counting circuit and the delay compensation circuit instead of loop filter and voltage control delay line, under a special control circuit, the DLL implement delay compensation. The DLL can be locked by only one adjustment rather than many consecutive processes unless the input clock changes. So, it costs less time to implement synchronization of input and output clock.In a Smic 0.18um CMOS process, its operation frequency range is 25MHz~300MHz at 1.8V. The maximal peak-to-peak jitter is 40ps. The DLL can be locked within 18 clock cycles.In addition to fast locking, the DLL has the following features: the DLL can provide three phase-shifted version of the source clock. The DLL can provide duty cycle correction on all output clocks such that clock outputs have a 50% duty cycle. The DLL can provide 1.5, 2, 2.5, 3, 4, 5, 8, 16 divide clock. The DLL can also provide 2 multiplier clock.