On-chip High Speed Low Jitter Clock Network Study And Design

With the continuous development of integrated circuit technology,the clock frequency of system operation is getting higher and higher.In some high-frequency ADC systems,some of the required clock frequencies have reached more than GHz.Generally,the off-chip clock signal has the problems that the duty cycle does not satisfy the sampling requirements and the frequency is single.The clock network completes the recovery of the off-chip clock signal,eliminating jitter,frequency synthesis,conversion,and driving.At the same time,a high-performance clock network should have the advantages of low jitter,low power consumption,and wide bandwidth.PLL-based clock generators are the most popular low-cost,high-efficiency solutions today,but as the clock frequency continues to increase,design difficulties and costs continue to increase.In view of these existing problems,this subject has made in-depth research and proposed a high-speed,low-jitter clock network based on a delay-locked loop.In this thesis,the related theories of Phase Locked Loop(PLL)and Delay-Locked Loop(DLL)are fully studied and analyzed.The clock network is designed based on the traditional delay locked loop.It can be divided into three parts: clock buffer module,duty cycle stability module,and multi-phase clock generation module.The clock buffer module adopts a fully-differential structure,which can effectively reduce the influence of noise and at the same time amplify the amplitude of the clock signal,thereby improving the driving capability of the signal.The duty cycle stability module is based on an improved delay-locked loop architecture design that can adjust the off-chip clock signal duty cycle to 50% to meet the system clock accuracy requirements.On the basis of comparing a variety of multiphase clock schemes,this paper selects a multiphase clock generation scheme based on D flip-flops,which can achieve frequency division of clock signals.After the external clock signal is processed by the clock network,a stable 50% duty cycle clock signal can be obtained as the control signal of the sample-and-hold circuit and the clock synchronization signal of other modules.The thesis adopts TSMC 0.18?m CMOS technology.Under the 1.8V power supply voltage,the input signal frequency is 500 MHz.The circuit can be simulated using candence software's spectre simulation environment.The simulation results show that the clock buffer circuit can play a role in improving the ability of the clock signal to drive,the jitter size of the clock buffer is 0.67ps;the clock stabilization circuit based on the delay-locked loop can achieve the 20%~80% duty cycle adjustment range,adjust Accuracy of ± 0.6%,the circuit jitter size of 1.42ps;multi-phase clock generation circuit based on the shift register can achieve two-frequency clock signal and phase shift function,jitter size is 0.26ps;the overall jitter of the design of this circuit is 2.35 ps,to meet the design requirements.