Design Of A Low-jitter Delay Locked Loop Circuit For TDC

With the increasing bandwidth and computing speed in the fields of communication and computer,digital signal processing and transmission are becoming faster and faster,meanwhile the conversion rate between analog and digital signals is also becoming higher.As a core clock circuit module in the digital integrated circuit system,its performance directly affects the overall chip performance level.In order to meet the requirements of complex circuit structure for the clock,more and more module circuits are integrated in the same chip,therefore,the design and implementation of on-chip clock circuit is becoming increasingly difficult.In this paper,the design of a low-jitter delay locked loop is proposed based on the constraint of the time-to-digital converter counting application.According to the small signal and noise transfer model of the analog DLL system,the key parameters of the DLL system such as the bandwidth and gain are determined,and the constraint relationship between the loop gain and the bandwidth is also quantitatively analyzed.Given the comparison among the noise transmission coefficient of the key modules,the low noise design strategy of the DLL system,such as the noise reduction within modules and the suppression of loop bandwidth,is provided.For TDC application,the key point is to optimize the circuit structure of the internal modules:Substitute the traditional phase detector with the novel double-edge-triggered phase detector to improve the efficiency of phase discrimination and increase the phase gain,so as to realize the fast response.Based on the ordinary differential charge pump,an improved differential charge pump is proposed to extend the output voltage swing and match the charge/discharge current significantly.Adopt the new differential voltage-controlled delay line with two improved single-stage differential cells to increase the gain linearity of the voltage-controlled curve and improve the output clock phase.According to the design method of layout matching and sensitive signal shielding like the centroid symmetry uniform distribution and addition of the ground wire on both sides of the sensitive signal,the key module circuit layout design is completed.Meanwhile,take the substrate noise,antenna effect,power/ground lines and the interference between modules or leads into considerations;the overall system layout is conducted to suppress parasitic parameters.Based on GSMC 0.18?m CMOS process,the schematic and layout design,simulation and MPW verification of the DLL are completed under the Cadence platform.The test results show that,in 1.8V supply voltage,the DLL's lock frequency range is 90MHz-240MHz,static phase error is 186ps@160MHz,the maximum output phase separation is 118.4ps@160MHz,the output duty cycle is 52%@160MHz,the output clock peak-to-peak jitter is 181ps@160MHz,the root-mean-square jitter is 23.8ps@160MHz.The DLL of this paper operates normally and can achieve a certain performance in the locked frequency range,however,the lock frequency range shifts down entirely and the measured output clock static and jitter performance worsens slightly compared with the simulation results under the same conditions.Analyze the problems existing in the testing process thoroughly,summarize the shortcomings in the design and testing process and eventually put forward the next improvement suggestion.