Research And Design Of Delay Locked Loops For TDC

With the rapid development of integrated circuit technology,the operating frequency of system on-chip(So C)has become higher and higher,and internal circuits of So C requires more stringent high-frequency clock signal.Therefore,the performance of on-chip clock circuit is increasingly concerned.Delay-locked loop(DLL)had performances including low output clock jitter,well loop-stability and faster locked speed,so which was widely used in the clock generstion ciricuit of time to digital converter(TDC).Therefore,a DLL was researched and designed for TDC in this thesis.The main contents including:Firstly,this thesis introduced the basic structure of DLL and discussed the key modules of DLL in detail.Simultaneously,this thesis analyzed the small signal model,noise transfer characteristics and lock range of DLL.Acorrding to noise characteristics and index requirements of DLL system,the relevant important parameters of DLL system were determined.Secondly,function modules,which included phase detector(PD),charge pump(CP),voltage control delay line(VCDL),mislock detection circuit and start-up control circuit,were designed in this thesis.To overcome the dead zone effect,the logic gate with enabling control function was adopted instead of the traditional delay chain.The CP adopted current feedback compensation structure in order to reduce current mismatch and output jitter.When the output voltage changed in the range from 0.39 V to 1.17 V,the mismatch rate of CP was less than 1.5%.To expand the delay range,the VCDL adopted the dual band structure,and the delay unit adopted the traditional single terminal structure.Finally,a DLL system was designed in SMIC 0.18?m CMOS process.The layout of DLL system was given,and the post-simulation of DLL was carried out.Post-simulation results showed that the DLL had a frequency range from 300 MHz to 500 MHz,a locked time of less than 0.5?s,a static phase error of less than 57.1ps,the peak-to-peak value of output clock jitter of less than 8ps and a power consumption of less than 9m W.