Research Of Design-for-test Of Phase-locked Loops Circuits

The phase-locked loop(PLL)is widely used in a large number of applications such as frequency synthesis,phase demodulation,clock distribution and timing recovery.It is essential for systems like wireless phones,optical fiber links and micro-computers.Thus,the design-for-test(DFT)of PLLs is of great significance to ensure the performance of the entire electronic system.The conventional PLL testability method which separates the structural test and performance verification,leads to the need of complex external test instruments to verify the performance of PLL under test,or it cannot check the structure fault in PLL circuits.And the test circuit is complex.The area overhead is large.Both the DFT technologies need high test cost and long test time,which reduce its value for engineering application.There are a few kinds of design-for-test methods which can complete both structure testing and performance evaluation,but most of them use independent test structure.Thus the test circuit is more complex.The test area overhead may be larger than chip area of the PLL.Its fault coverage and resolution of jitter measurement is also need to be improved.Therefore,based on the PLL DFT scheme considering structural test and performance evaluation,we mainly focus on the research of fault detection and jitter measurement on-chip using a same DFT circuit with high fault coverage and jitter measurement resolution.The main works of this thesis are as follows:(1)The relationship between structure fault and jitter of CP-PLL is studied.Based on the system theory model analysis,the behavioral model and the transistor level model,the impact of structure fault on jitter of CP-PLL is qualitatively and quantitatively analyzed.(2)System design and verification of a low cost DFT structure of CP-PLL which provides both the fault detected and timing jitter measured.A time-to-digital converter(TDC)with high resolution is proposed in the DFT structure for achieving fault detection and jitter measurement of PLL on-chip.In which it uses the PLL under test as the time difference detector,thus the detection range is very wide.A signal processing unit is also employed for automatically transforming mode among the fault detection,jitter measurement and clock generation.Thus the testing process is very simple.And only one external signal is used to enable the test,which minimize the demand for external test resources.It is verified that the structure has little influence on the performance of the PLL,and it has high fault coverage and measurement resolution.(3)Design and verification of an all digital fault detection methodology based on defect-oriented-test(DOT).It proposes a new simple PFD structure to generate test signals on chip and control the whole detection process.Combined with the most existing blocks in CP-PLL as the input stimulus generator and fault feature extracted devices for testing evaluation,the area overhead is reduced.With a little modification on the digital part of the CP-PLL,it has a little influence on the performance.The additional test structure is all digital and easily implemented with 14 DFFs and 3 MUXs.It is verified that the fault coverage of the structure can reach 98.75%.(4)Design and verification of an all digital jitter measurement methodology based on TDC.In the structure,by proposed a new TDC structure for on-chip jitter measurement of CP-PLL,it achieves a small test area overhead.By employed a new PFD structure to detect the time difference,it is more suitable for detecting a timing jitter which is extremely small or big.Used the proposed self-referred circuit,it does not need an additional jitter-free reference signal for on-chip jitter measurement.Thus it reduces the test cost.The proposed DFT structure only has a minor modification on the digital part of the CP-PLL,thus it has a little adverse influence on the circuit performance.It is verified that it can detect a timing jitter of 0.78ps with a measurement error of 5.78%The DFT structure of PLL is built on the TSMC 0.13-?m CMOS technology.The chip area is 575.7×582.8?m~2,in which the additional test circuit accounts for 0.78%.The fault coverage is 98.33%.The RMS jitter of CP-PLL is 17.25ps.Compared to the results of test equipments,the proposed DFT structure gets a relatively high resolution of 0.9865ps with a measurement error of 11.91%.Results demonstrate that the effectiveness of the proposed DFT structure of PLL with high fault coverage and jitter measurement resolution.It greatly reduces the test area overhead.