A Multi-phase Output Delay Research And Design Of Phase-locked Loop

With requests of Ultra Large Scale Integration and high speed signal processing, designing on-chip clock generating circuit becomes key step to realize high-performance integrated circuits. DLL (Delay Locked Loop), based on voltage-controlled delay line, gets special attention for its good performance. DLL precisely divides input clock, generate different delay signals to satisfy different modules'requirement on SOC. DLL has advantages of unconditional stabilization, fast locking speed, high dither resilient ability, precise clock locating, so when designing high-performance multiple-output-phase signals, DLL is superiorly used to PLL.The DLL is designed and implemented as multiple-output-phase clock generator, which generates high-speed, stable, wide-frequency operating parallel clocks for DVI receiver digital system, it can also output 40 phase clocks covering 25MHz-165MHz, it is DVI standard compatible when applied to DVI receiver.DLL's loop bandwidth is analyzed based on DLL's mathematic model system, the thesis studies root causes which influence jitter, discuses source of system noise and resolving way.The DLL reconstructs false lock prevention indicator, makes it co-work with Phase Detector to generate signals which indicate delay line status, the signals then control delay time of voltage-controlled delay line. Their co-working makes lock speed faster and has broad harmonic lock prevention scope of DLL; It has good linearity, strong noise immunity by using differential delay cell and negative feedback self-biased charge pump, self-biased delay line; according to requirement of low jitter at output, LDO is designed to provide 1.2V power for analog modules of DLL, which can depress power noise.After theoretically demonstrating loop bandwidth with mathematic model system and making behavioral simulation with MATLAB, the DLL and every module are designed and simulated with both HSPICE and SPECTRE simulators, the DLL designs layout placement and detailed requests after taking mixed-signal layout performance, process characteristic, ESD(Electro-Static discharge), noise immunity requests into account, post-layout simulation is done, then circuit and layout are re-optimized for high performance. Experiment results show that DLL's output has low jitter, the DLL can meet the requirement not only the design specification but also for customer application.