Research And Design Of Delay Locked Loops For Clock Generator

Clock generation circuit is an indispensable module in integrated circuit system.The quality of clock directly determines the performance of the integrated circuit system.Compared with phase locked loop(PLL),delay locked loop(DLL)has faster locking speed,better clock jitter performance and better loop stability,so it is widely used in clock generation circuits.Based on those,a delay locked loop was desined for clock generator.The main work including the following:Firstly,on the basis of analyzing and discussing principle,small signal model and noise transfer model of DLL,the loop bandwidth and key module circuit parameters of DLL were confirmed in accordance with loop bandwidth and key module circuit parameters of DLL.At the same time,the non-ideal characteristics and noise characteristics of sub-module circuits and design method was given to reduce the jitter of the system output clock.Secondly,a high power supply rejection ratio(PSRR)high-order temperature-compensated bandgap voltage reference(BGR)was designed by adopting high-order temperature compensation technology and low dropout regulator(LDO)technology.Simulation results showed that the temperature coefficient of the designed BGR is 2.36ppm/?C in the range of-40?C to 125?C and the PSRR is-125.63 dB at low frequency.Thirdly,sub-module circuits of DLL were optimized.For phase detector,the dead zone of phase detection could be eliminated by adding delay buffer in the delay path,and two feedback signals had the same delay to the output by optimizing NOR gate circuit.For charge pump,non-ideal effects of charge injection could be restrained by current wheel main circuit with virtual switch transistor,and charge and discharge current matching could be improved by adopting bias circuit with current compensation and negative feedback current compensation circuit.For loop filter,by adding an initialization circuit,error lock in the operating frequency range of the system could be avoided,and the locking speed of the system could be improved.By adopting LDO that provided the operation power of voltage-controlled delay line,the effect of power supply voltage fluctuation on operation frequency range and output clock signal jitter could be reduced and the suppression ability of power supply noise could be effectively improved.Finally,based on the designed sub-circuits of DLL and SMIC 0.18μm CMOS process,a DLL was designed.When the dynamic power noise with a swing of 100mV@1MHz was added to the power supply voltage,the DLL achieved these performances including the locking frequency of 500MHz~800MHz,the locking time of less than 0.4μs,the locking error of less than 5.5ps,the clock jitter of less than 6ps,the duty cycle error of less than 1%,and the power consumption of less than 6mW.