| Today in many applications such as network switches, routers, multi-computers, and processor-memory interfaces, the ability to integrate hundreds of multi-gigabit I/Os is desired to make better use of the rapidly advancing IC technology. With many high speed I/Os integrated on a chip, the wire count, component count, and power budget of a system can be significantly reduced, allowing for both reduced costs and expanded capability. Although previously published designs have achieved multi-gigabit bandwidth per channel, the area and power consumption are too large to make terabit integrated circuits feasible.; In this thesis, an efficient 110 and clock recovery design is presented. In a 0.25-μm CMOS technology, the circuits operate at 4-Gb/s, occupy 0.3-mm 2, and dissipate 180-mW on a 2.5-V supply. Keys to achieving these numbers are a set of circuit techniques applied to the transmitter, the receiver, and the timing circuits. In addition to power and area, resistance to digital noise sources is also critical to enable integration in a VLSI environment. A low-swing input-multiplexed transmitter is used to serialize low-speed data without the speed limitation of traditional input-multiplexing or the area and power penalty of output multiplexing. Since this I/O is intended to be part of a large digital system, pre-emphasis filter is used to drive a backplane with 40-in of PCB trace and two connectors (or other media with a similar loss). A mathematical analysis of the channel and the filter is presented, showing that a 2-tap FIR filter is adequate in such a case. A capacitively trimmed sense amplifier is used to cancel the receiver offset without sacrificing the speed. This technique increases both the voltage and timing margins, allows small receivers to be built, decreases the power consumption, and increases the input bandwidth. A supply-regulated inverter delay line is used to implement the multi-phase delay-locked loop. Compared to source-coupled delay lines, it dissipates less power and is more portable and easier to design. By regulating the delay line supply with a voltage regulator, the jitter is also significantly reduced. Finally, the Sidiropoulos dual-loop architecture is adopted for the clock recovery. A current-mirror circuit topology is used for both the phase multiplexer and the phase loop architecture is adopted for the clock recovery. A current-mirror circuit topology is used for both the phase multiplexer and the phase interpolator to achieve a high bandwidth and a good phase linearity. This circuit topology helps the overall timing budget by reducing the receiver clock jitter and dithering. The above circuit techniques were incorporated into two test prototypes, whose experimental data will be described in detail. |
