Research And Design Of Wide-range Clock And Data Recovery Circuit

People’s requirement of speed and amount of communication grows with everypassing since human steps in information era, which make communication technologybecome hot spot of technological development. Serial links has become the most populartransmission mode because of its advantages, such as high speed, long distance. Clock anddata recovery (CDR) circuit is responsible for serial link systems to recovery clock andretime data. What’s more, with the increasing demand of speed and quality ofcommunication, CDR restricts the speed and transmission quality of transmission, whichmakes it becomes as research focus and hot spots for scientists and engineers at present.This paper studies wide-band clock and data recovery circuit used in high-speedoptical fiber communication systems. First, the research status of CDR is introduced, andthe need for wide-band CDR circuits is discussed. Second, the different structures of clockand data recovery circuits are summarized and compared to decide which is suitable forwide-band used, and design a new circuit structure. Finally, we do system-level designincluding frequency band selector, low pass filter, new FD and PD.A2Gbps to8Gbps continuous-rate CDR circuit employing a multi-modevoltage-control oscillator (VCO), a frequency detector and a phase detector (FD&PD) isdescribed. A new automatic frequency band selection (FBS) without external referenceclock is proposed to select the appropriate mode and also solve the instability problemwhen powering on. The multi-mode VCO and FD/PD circuits which can operate at full-rateand half-rate modes facilitate CDR with four operation modes. The proposed CDR structurehas been modeled with MATLAB and verified in the SMIC180nm Mixed Signal LowLeakage&RF1.2/1.8/3.3V(1P2M~1P9M) process in Hspice.