Applied To The Mobile Payment Chip Research And Design Of Clock Recovery Circuit

As RFID technology continues to progress, it has been widely used in various fields.RFID technology-based mobile payment industry in recent years has been booming,and the bottleneck is that the complex electromagnetic environment of the phone’s lead to signal attenuation, reducing the success rate of communication between the RFID transceiver and readers. Currently on the market, many solutions are either too costly or communication reliability is low. So, a low-cost, high reliability of mobile payment technology solutions called QSIM program,was put forward by Quanray Electronic Co. Ltd in Shanghai. The main purpose of this paper is to design an clock recovery circuit applied on the RFID transceiver chip in the QSIM system. Circuit design is based on smic0.18um EEPROM2P4M process,and the circuit structure composed of a comparator used to exact clock from antenna signal, and phase-locked loop used to lock the clock.Firstly, the design method of loop parameters of phase-locked loop and noise transfer function of each module are analyzed.Then the voltage-controlled oscillator structures applied in the clock recovery circuit are summed up. After comparing with the advantages and disadvantages of different delay cell structures used in ring oscillators, single-ended current-steering delay cell structure is adopted. In addition, the design method of low jitter ring oscillators was discussed,and then a low-cost, low-power ring oscillator was designed.secondly, a comparator with strong ability of anti-noise and weak depedance of process is proposed.At the end,each block of PLL is desgined and the CRC simulation results of each instruction are shown.Finally, the chip test results are provided. Phase drift during the instruction groove time, PA transmitting time and the time when only carrier from reader is on the atenna, is about20°,70°,10°respectively.At the last,design optimization program is proposed after analyzing the test results.