Clock And Data Recovery Circuit Design Of Optical Receiver Chip

Optical fiber communication has a lot of advantage,such as large capacity,strong anti-interference ability,long transmission distance,energy saving and so on,which make it the hot research topic at present.Clock and data recovery circuit is required in optical fiber communication to restrain jitter by extracting the clock from the data signal and retiming the data signal.The main stream of our country in the optical fiber communication is 2.5Gbps at present,along with the speed and requirements of the the optical fiber improve,optical fiber with 10 Gbps transmission rate will be the mainstream in the future.So the main objective of this paper is to design a clock and data recovery(CDR)chip with a center frequency of 10 Gbps.This paper designs the clock and data recovery circuit based on phase-locked-loop structure,which includes frequency detector(FD),phase detector(PD),low-pass filter(LPF),charge pump(CP),voltage controlled oscillator(VCO)and the retime module.This paper uses LC VCO of low noise structure to reduce jitter accumulation and generate high-frequency clock signal.The reference level limits are set up in the charge pump module to constrain the controlled voltage in the linear zone of the voltage controlled oscillator.This paper adopts a new type of frequency detector to get a large frequency capture range of 1.35 GHz which selects frequency by decreasing voltage.Phase detector optimizes zero crossings by useing front D flip-flop and keeps the clock signal sampling in the middle of the data bits,which provides the largest margin for jitter and uncertain factors.Phase detector and frequency detector can switch after they finish working,which can shorten capture time and improve work efficiency.This paper adjusts the loop parameter to make the system locked.After the input data signal is retimed by the extracted clock,the jitter of output data signal gets greatly reduced.This paper simulates each component of clock and data recovery circuit,makes the whole simulation in Cadence,designs the layout based on TSMC 0.18?m process and gives the post layout simulation in the end.The pre-layout simulation result shows that the power consumption of this clock and data recovery circuit is 90 mW over the power supply voltage of 3.3V,the phase noise of recovered data signal is 87.5dBc/Hz,and the voltage control gain of VCO is 1.08GHz/V.After the system is locked,the peak-to-peak jitter of output clock is 3ps,the peak-to-peak jitter of retimed data signal is 4.5ps.The area of this chip is 300?m×500?m.The post-layout simulation result shows after the system is locked,the peak-to-peak jitter of output clock is 6ps,the peak-to-peak jitter of retimed data output is 10 ps.Compared with 15 ps of input data jitter,this clock and data recovery circuit has a good jitter suppression effect.