Ethernet Controller Physical Layer Clock Recovery Circuit Design

With the rapid development of the information age, the network have been developing rapidly, and wired network information transmission carrier is an indispensable part in. Rapid growth not only satisfies people network bandwidth to speeds requirement, and also provides a stable and reliable transmission carrier. The reliability of the network consists of the data transmission appeared in the process of throw frame rate, data error correction ability, ber etc indicators to measure. In order to ensure that data can receive in receiving process stable reliable data, and improve the data transmission rate, a high-performance clock/data recovery circuit is we need to seek a function modules.This paper use a method based on PI structure of the clock recovery circuit, this structure used to 10M/100Mbps the physical layer of Ethernet chip, provides a stable and reliable clock system. This clock recovery circuit is popularly used the main modules including PFD, CP, LPF, VCO and 10/11 two-mode Divider. The paper presents the design phase lock loop circuit output the 250MHz center frequency, in the 600KHz deviate center frequency phase noise in -108dBc/Hz, with quickly lock time high-performance clock recovery circuit by power of DC 2.5V.This design content mainly includes, design of a type D flip-flop by master-slave composed of high-speed PFD circuit, this triggers a high-speed flip ability, can work in high frequency; Design the current rudder switch type, the charge pump charge pump have fast charging and discharging characteristics; Design a current hunger type differential oscillator, the oscillator is using 11th level difference delay unit, the output of 11 different phase 250MHz clock frequency used to recover data after the grade circuit; Design a 10/11 two-mode divider for the VCO output frequency, the clock frequency 250MHz after 10 divide for the PFD frequency phase discrimination.This paper based on the simulation is Spectre software platform completed, completed the Ethernet controller Physical layer clock recovery circuit, the system simulation verified the feasibility of clock recovery circuit. Through the simulation result, determine the clock recovery circuit performance meet Ethernet requirements.