Design Of 40Gbps Full Speed Clock And Data Recovery Circuit

Information and communication technology has been affecting our daily life.The development of technology makes a large number of modern electronic devices can generally use wireless communication technology.With the development of communication technology,the signal transmission rate has been greatly improved,and the needs of the industrial application and consumer have put forward higher requirements for information communication.In high-speed data transmission,serial communication technology has gradually become the main way of data communication.Clock and data recovery is the core module in the receiving system,which determines the performance of the receiver.In this paper,a 40 Gb/s high-speed clock and data recovery circuit based on phase-locked loop is designed in TSMC 40 nm LP CMOS process.The main modules include: phase detector,V/I converter,loop filter,LC voltage controlled oscillator and buffer.For the convenience of design,the jitter performances of nonlinear CDR are analyzed in detail,and a jitter model is constructed to guide the circuit design.In this design,the improved Alexander phase detector is used in the phase detector module.In order to make the circuit work on 40 Gbps,a large number of D-flip-flops,latches and XOR gates with current mode logic structure are used.The XOR gates structure of the phase detector is symmetrical and connected with the V/I converter by means of current mirror,which can improve the working speed of the circuit and reduce the current mismatch effectively.In order to further improve the working speed of the circuit,the traditional Alexander phase detector structure is improved.The input end of XOR gates is changed,so that the structure of the circuit becomes more symmetrical.At the same time,the influence of the parasitic capacitance of XOR gates on the sampling port can be reduced,which is conducive to reducing the clock shift.The VCO module adopts inductively capacitance VCO.For the key indexes such as tuning range,linearity and phase noise,the parameters of Q value,cross coupling pair and tail current tube are optimized.At the same time,the array of varactor is used to increase the tuning range of VCO.This paper presents the circuit design,pre simulation,layout design and post simulation results of 40 Gbps CDR.The overall layout area of the circuit is 525 ?m×525?m.The post-layout simulation results show thatthe clock data recovery circuit can recover the clock signal and data signal successfully from the 40 Gbps input data under the supply voltage of 1.1V.In TT process corner,the tuning range of VCO is 38.5GHz-40.25 GHz,and the phase noise is-95.97 d Bc/Hz@1MHz when the frequency of oscillation is 40 GHz.The lock time of the CDR is 65 ns.The recovered clock has a peak to peak jitter of 0.385 ps,namely a relative jitter of 0.0154 UI,and the recovered data has a peak to peak jitter of 1.79 ps,namely a relative jitter of 0.0716 UI.