Ultra-high-speed Clock Recovery Circuit Circuit Design

With the development of the information industry, we need high-speed and broadband interconnection to convey information with each other. To accommodate this trend, optical communications are taking the place of traditional cable communications. Also this trend motivates research on low-power, low-cost and monolithically integrated optic-fiber transceivers. A critical task of such a receiver is the recovery of the clock embedded in the data stream. Then, the recovered clock retimes the data and removes the jitter and distortion in the data. Consequently, the clock recovery circuit (CRC) is the key part in optical communications and other high-speed serial communications.The research objective of the thesis is to analyze, design and implement a high-speed CRC for STM-16 bit-rate (2.488Gb/s) optical fiber receivers that can be readily implemented in 0.35 μm CMOS technology. Because of the limitations of the 0.35 μm CMOS technology,we employ a full analog structure which is composed of a preprocessor and a phase-locked loop(PLL). This kind of circuit can wok at high speed. The preprocessor can extract clock information from NRZ data stream, which consists of a delay cell, a multiplier and a narrow-band filter. The analog PLL contains three basic components: a Gilbert multiplier PD, a passive filter and a three-stage ring oscillator.The thesis presents basic principle of CRC and rounded circuit design, simulation results, layout design and testing results of a PLL type CRC, which is incorporated in a optic-fiber receiver chip. The testing results indicate that the main functions of the CRC are realized and primarily meet the task of the design.