Low power and thermal issues in VLSI synthesis

The VLSI circuits design industry is facing a similar diffculty to that seen years ago, when CMOS technology replaced TTL. This diffculty is that the extremely high power dissipation prohibits further increasing the integration density. In order to keep benefiting from the next generation of VLSI manufacturing process, low power design becomes a must for all the future VLSI circuits. In this dissertation, we will present a few essential advances in design automation of contemporary VLSI circuits for the power and thermal challenges.;Our investigation of the low power and thermal-aware design methodology is conducted in several different design phases during standard VLSI design flow. We first investigate two high-level synthesis techniques that take the leakage power and dynamic power as additional design metrics, respectively. By adding new constraints and changing the objective functions of the classic high-level synthesis algorithms, including resource allocation and register binding, the total power consumption of the circuits can be budgeted more efficiently by our proposed techniques.;We also investigate the low power design techniques during sequential circuit optimizations, which are usually performed after finishing the high-level synthesis. We propose a unified linear programming framework to accommodate clock skew scheduling, dual threshold voltage assignment, and gate sizing. In this way, sophisticated trade-offs among these design metrics, such as sizes, threshold voltages of gates, and the clock arrival times of flip-flops in circuits are determined by a more systematic mechanism, i.e., the linear programming solver.;Our treatment of low power design methodology in this dissertation is in a more systematic manner instead of developing individual pieces. For example, we investigate the utilization of clock skew scheduling technique for both high-level synthesis and RTL level optimization. Not only the effectiveness of the proposed low power techniques is paid attention to, we also propose faster algorithms for solving embedded sub-problems, such as clock skew scheduling. These efficient algorithms are the basis for the feasibility of proposed low power design techniques.