Timing Optimization Using Clock Skew Scheduling For VLSI

In digital IC(Integrated Circuits) design,the clock signal is most important. It plays a critical role on the function, timing and stability of synchronous digital systems. Methods of traditional or early clock tree synthesis are expected to obtain a zero skew clock tree. However, it is proved that zero clock skew is not optimal strategy. Clock skew can be used to improve timing performance and reliability of circuits. The main contents of this thesis can be divided into the following sections:(1) Firstly, it introduces the origin of clock skew and the impacts on timing and stability of circuits. Traditional strategy of clock tree synthesis is also introduced. Relationships between clock skew and minimum-period of circuits are concluded from the operating principal of flip-flops and lathes.(2) Secondly, Pipelining and Retiming techniques of traditional zero clock skew optimization methods will be introduced and analyzed. It explores the application fields and shortcomings of these two optimization methods. And then Clock Skew Scheduling algorithm is presented to improve timing performance.(3) It mainly analyzes and studies the impacts of Clock Skew Scheduling(CSS) on circuit timing and stability. The implementation of CSS will be analyzed. With the help of IBM CPLEX optimization software, the ISCAS’89 circuits are chosen as benchmarks to verify and test the algorithm of CSS. Experimental results show that compared with the conventional zero clock skew strategy, the average improvements in minimum clock period for flip-flops circuits is 28% and for latches circuits is 14%.(4) This thesis analyzes the impacts of Clock Skew Scheduling on circuit stability. The compensation method and cost function method optimize stability will be implemented and solved by IBM CPLEX software. Experimental results show that the two methods have improved stability at the expense of timing performance. It is impossible to optimize timing performance and reliability at the same time.(5) Usually, The Delay Insertion method is used to fix timing violations and improve stability during IC design. This thesis proposes the Delay Insertion Using Clock Skew Scheduling method to optimize timing performance and improve circuit stability. Under the help of CPLEX, the optimization method is implemented in details. We can make use of this method to compensate the variations during chip design and manufacturing process variations caused by external factors. For ISCAS’89 circuits’ experimental results show that circuit stability can be improved about 10% under the minimum clock period using Clock Skew Scheduling method.