A Study Of Techniques For High Performance Clock Distribution And Clock Deskew

The design optimization of the clock distribution network is one of the most important and most challenging tasks in high-performance digital systems. This paper, aimed at the reduction of power consumption of clock distribution network, goes into the clock skew adjustment technology and the power optimization of clock distribution network. An all-round and all-level clock distribution scheme based on phase alignment has been proposed to solve the problem of high complexity and power consumption of the traditional clock system, on the basis of which an in-depth study of the key circuit in the implementation of this clock distribution scheme is conducted. This scheme doesn’t only avoid the high power and area consumption of traditional clock distribution network which is based on the balance of clock delay, but can also enable the effective and timely adjustment of the dynamic clock skew resulted from PVT and other environmental problems. An analogous self-timing system is employed in the leaf node of the clock distribution network in this scheme to fundamentally eliminate the adverse effects caused by clock skew and effectively reduce the power consumption of the clock network. The main job and innovation done and achieved by this paper are as the follow:1. This paper goes into the essence affects of clock distribution network on synchronous circuit. Aimed at the high complexity and power consumption of the traditional clock system based on the balance of clock delay, this paper puts forward an all-round and all-level clock distribution scheme, which can effectively improve the flexibility of clock distribution network design, avoid a series of problems caused by the traditional design of global clock, and reduce the complexity and power consumption of clock distribution network; the simulation experiment results suggest that, compared with the path-delay distribution scheme adopted by traditional balanced clock, the all-round and all-level clock scheme proposed by this paper has the following advantages: for high-frequency large-scale digital IC chips, no matter from the time design of clock network, the difficulty level of hardware implementation, or the power consumption of chips and chip size, the scheme raised in this paper is better than the traditional balanced-delay-based clock distribution scheme. It has greatly reduced the designing time of clock network and the volume of inserts of clock buffering, and also has significantly reduced the area overhead, as well as the clock power consumption of the high-frequency VLSI system.2. On the basis of the proposed all-round and all-level clock distribution scheme, this paper presents the scheme-supporting phase detection of distributed clocks, the adjustment method of centralize fast clock skew. Meanwhile, a new high-precision & low-consumption clock deskew circuit, Direct SMD-DLL, is designed and realized in this paper. The traditional clock deskew circuits can be mainly divided into the SMD-based and the DLL-based. DLL, though of high adjustment precision, has a long blackout period and high power consumption; SMD has a shorter blackout period and lower power consumption, but the precision is poorer, and it can’t self-adapted to and adjust the dynamic clock skew caused by PVT and other environmental problems, nor be used in high-performance VISI represented by high performance micro processor. To solve the problem of the traditional clock skew adjustment circuit, this paper has presented a new type of clock deskew circuit, where rough adjustment is implemented with Direct SMD and fine adjustment is implemented with DLL. The relevant circuit design and the board layout have been implemented too. Post-simulation shows that, compared with some of the newly-presented clock deskew circuits, this new type of deskew circuit has exceeded the contrasting circuits in blackout period, chip size and consumption the contrasting circuits, and can help to realize the rapid, large-scaled and high-precision static clock skew adjustment.3. This paper has presented and realized a new phase linear detector of low static error and zero dead-zone, which can effectively satisfy the high-precision global clock skew circuit. Phase linear detector is a key component in the skew adjustment circuit of the global clock. The precision and sensitivity determines the compensation precision of the whole dynamic clock’s skew adjustment circuit. To solve the problems of precision, sensitivity and the contradictory dead-zone eradication, this paper, with an overall consideration to the advantage of binary and linear phase detector, has presented and realized a new hybrid dead-zone-free phase linear detector. Experiment results show that, compared with other phase linear detector in common use, the new phase linear detector presented is not only of high-precision as the ideal linear phase detector, but is also dead-zone-free as binary phase detector. As a result, in addition to the efficient improvement of detector’s precision, dead zones can also be eradicated. Based on this, it can provide effective circuit support for the implementation of high-precision skew adjustment of global clock.4. This paper has presented a fast clock skew adjustment scheme applied to regional clock distribution, and designed and realized the relevant circuit. The circuit, based on the characteristics of regional clock distribution and under the action of a reference clock, has achieved the auto-correction of clock skew at an extremely low circuit cost. Guided on the reference clock, the circuit uses up-drawing and down-drawing tubes to implement relevant phase adjustment of the abnormally fast or slow clocks. The simply structured circuit needs only 10 transistors for each level of adjustment circuit. Through proper size design of each level of adjustment transistor, a high-precision and extremely fast clock skew adjustment can be realized. The circuit experiment result suggests that the time skew produced by this clock skew adjustment circuit to the original phase is almost negligible. With a proper choosing of the size of different transistors, this circuit can successfully adjust up to 50% phase deviation of the clock period. Besides, through Monte Carlo analysis, it can be found that the circuit can still work normally even when the mains voltage fluctuation reaches 20%.5. According to the all-round and all-level clock distribution scheme raised by this research, a structure similar to self-timing circuit is adopted in the final level to fundamentally avoid the clock skew and the heavy consumption of the traditional clock distribution network at the final level of distribution network. This paper has presented and realized a sequential logic similar to self-timing, of which the timing signal is formed locally to avoid all the problems and costs caused by high-speed clock distribution. Since the clock period of a synchronizing system is determined by the lowest path of the pipeline sequence, while the computed result of each pipeline stage is sent to the next stage as soon as it’s finished in the self-timing system, the equivalent clock period of this self-timing logic equals to the average delay of each pipeline stage. In contrast to synchronous sequential logic, such self-timing logic can effectively tap the circuit potential and improve the system performance. Also, this self-timing circuit has obvious advantage over the synchronous circuit in power consumption. Firstly, self-timing circuit can avoid the huge consumption caused by clock distribution, clock buffering and clock driving; secondly, timing signal, produced only when necessary, is in fact a most granular gated clock, can achieve better consumption reduction than gated clock in a synchronous system. Post-simulation of circuit layout shows, this self-timing circuit, with an extremely small circuit area, has effectively achieved the goal of self-timing. The establishing time is very short, close to zero, and shows an abrupt rising edge in the waveform, indicating the excellent performance of it.In conclusion, this paper has conducted overall and in-depth study on the optimization and clock skew adjustment technology of clock distribution network; implemented the general and local high-performance clock skew adjustment circuit; presented and realized an self-timing asynchronous circuit to solve the clock skew of the clock distribution terminal and significantly reduce the power consumption of clock system. This study, related to the improvement of the performance, reliability and stability of high-speed chips under nanometer technology, is of certain significance in both theory and engineering for the performance improvement of synchronous digital hierarchy and the reduction of clock power consumption.