The Application Of Clock Mesh In ASIC Design

Since the first transistor has emergence in 1947, IC industry has followed Moore's Law for nearly half a century. With the improvement in IC technology nodes, the chip's operating frequency is increasing, and the requirements of clock skew is more and more stringent, the clock's design has become a huge challenge to the chip designers. According to ITRS (International Technology Roadmap for Semiconductors) 2009 expected, in 2012 the clock frequency of ASIC (high performance) will reach 5.3GHz. In the high-speed chip systems, clock tree synthesis (CTS) has become extremely difficult to distribute the clock signal to each sequence in near zero skew request, therefore the clock mesh structure which is always used in microprocessor gets attention and research.Clock mesh is a kind of clock distribution structure with mesh-shape, currently used on the microprocessor chip in the industry, not yet been used in the field of ASIC and SoC Design. In this paper, clock mesh structure is used to an ASIC chip with four sizes. Clock skew of four sizes are get and compared to the skew of clock tree structure. The data shows that clock skew of the chip used clock mesh structure is 50% smaller than the chip used clock tree structure.Then the relationships of total power and total wire length to the mesh size are obtained. The total wire length on chip increases with the clock mesh size. The total power first decreases and then increases as the clock mesh's size increase, minimum point of the total power appears. This provides a basis to choice the best size of clock mesh in the ASIC design which is used clock mesh structure.