| A fundamental challenge in low power IC design is the unfavorable tradeoff between circuit speed and power. The impact of clock distribution on system speed and power exemplifies this challenge. Another increasingly important challenge as a result of the deep submicron technology is that chip performance and reliability are becoming extremely sensitive to process variation and noise effects. This thesis investigates some of the issues in dealing with these challenges.;Previous research in clock tree routing bears the underlying assumption that zero-skew or smaller skew is better for system performance and reliability. After taking a closer look at clock skew and its properties, we see that this assumption is not valid. Allowable negative skew can be used as useful skew to mitigate the unfavorable tradeoff of circuit power and speed. We therefore formulate the problem of Useful-skew Clock Tree Synthesis. We present a useful-skew tree (UST) algorithm to minimize both the clock and logic power.;In a realistic environment, clock signals behave far from ideal clocks. Due to process and operating conditions, the timing fluctuations of clock signals are inevitable. They are known as clock jitter. Furthermore, the exact nature of clock jitter is not known. It is very difficult, if not impossible to predict their behavior. In the presence of clock jitter, zero-skew or small skew will not necessarily result in reliable clock operations. In fact, non-zero allowable skew can sometimes be used as safety margins to guard against clock jitter. We present a solution in two-phase synchronous systems to optimize the clock tree and maximize the safety margins such that clock operations are tolerant to clock jitter.;Clocking has always been the most critical issue in the performance of synchronous systems. With increasing clock frequency and integration density, power dissipated by clock distribution has also become a major source of total system power dissipation. As a result, clock tree synthesis becomes not simply a layout problem. For low-power clock distribution, it has been found that the distributed buffer scheme should be preferred. Instead of increasing wire widths or lengths to reduce skew which results in increased power dissipation, distributed buffers can reduce skew and save wiring capacitance and clock power. However, due to process variation effects, buffer delays may introduce additional skew. We present an optimization solution to separately size the PMOS and NMOS devices in buffers. Regardless of process conditions, allowable skew constraints are satisfied. |
