The Reconfigurable Chip Clock Tree Synthesis Technology Based On65nm

With the rapid development of IC architecture and technology, the characteristic dimension shrinks, the physical design become more and more complicated, the design methods of the integrated circuit should meets stricter requirement. As a universal time reference to digital circuit, the clock signal plays more and more important role in designs. Clock tree is a transmission network of clock signal, which influence the function and performance of system. In the phase of the physical design of the integrated circuit, Clock Tree Synthesis is performed to meet the timing of the circuit, need to considered how to make the clock signal transmit and arrive at the registers at the same tine, and how to decrease the amount of the inserted buffers in the clock network. With the higher frequency and the more complicated architecture of the clock, Clock Tree Synthesis has become an important procedure in the Deep Sub-Micron back-end design.This thesis based on the design of reconfig chip, using IC Compiler provided by Synopsys, discusses the flow of auto Clock Tree Synthesis methods in the Deep Sub-Micron physical design. IC Compiler, which belongs to Synopsys, integrates the function of floorplan, placement, clock tree synthesis and routing. This paper firstly introduced the concept of clock, timing and some important elements that can affect the performance of the clock tree, such as clock delay, clock skew, clock jitter and transition time, back-end designers who better understand the clock and timing of the design can do better for the physical design. Especially, in the clock tree synthesis stage, the knowledge of the clock and the type of the clock in the design is very important.This thesis then introduced the theory of Clock Tree Synthesis which based on the tool IC Compiler. Simply introduced the base flow for Clock Tree Synthesis, and described the file of timing constrains, and then introduced the analysis for skew and timing after Clock Tree Synthesis in detail. Finally, discussed the approaches to decrease the clock skew, adjust the clock delay and the using of useful clock skew, with the design of RECONFIG chip under the TSMC65nm technology process, based on the IC Compiler physical design process.