Research On Clock Network Optimization Based On 55nm Process ASIC Chip

With the rapid development of the integrated circuit industry and the continuous reduction of integrated circuit technique,the scale of digital integrated circuits is increasing,and the timing requirements are becoming more and more strict.This causes the clock structure of the digital integrated circuit to become more complicated and the frequency to become higher.In the physical design of digital integrated circuits,the clock network is the most important additional generation,because the clock signal provides a time reference for data transmission,so for the digital chip design,the quality of the clock network is not only related to the timing result of the design,whether it can meet the requirements,and determine the advantages and disadvantages of the chip design in the physical implementation process.This paper takes the Beidou baseband algorithm control ASIC chip as an example.Designed using Global Foundries 55nm(GF 55nm)process,the chip area is5.2mm * 5.3mm,the scale is 16 million gates,including 144 IP,operating frequency is 250 MHz,the operating frequency is high under this technique,and the clock structure of this design is quite special,and the clock network cannot be designed by traditional design methods.Therefore,according to the characteristics of the clock structure,this paper proposes a method to design the clock network by forcibly configuring the clock unit of the critical path before the clock network is synthesized.This paper mainly studies the optimization of the logical layer clock network by adjusting the clock constraint file structure,and optimizes the physical layer clock network by forcing the configuration to obtain a high-quality clock network design method.In order to make the ASIC chip timing sign-off and reduce power and area,this paper uses the following clock network design method:(1)Pre-analyze the design through the clock structure,and select the clock unit that needs to be forcedly configured.On this basis,rebuild the clock constraint file,optimize the clock network on the tool logic structure,and shorten the design cycle by more than 33%.(2)In the standard cell placement stage,the clock network design is intervened in the physical structure by forced configuration,which greatly shortens the length of the wire,and the clock delay is reduced by more than 50% on average.(3)Based on the traditional iterative optimization design idea,expand the optimization coverage,optimize the clock network only in the clock tree synthesis stage,extend to the layout stage,and iterate the design by rationally designing the parameters of various constraint files andthe tool flow.Optimization,and finally get a reasonable clock network,by this method to reduce the total design power consumption again,from 180.0832 m W before the iterative optimization to 164.3517 m W.The simulation results show that the clock network is designed by the logic layer and the physical layer jointly optimized method.The clock skew is optimized by71.83% on average,and the total violation value of the setup time is reduced from-26.437 ns to-2.610 ns.The Total Negative Slack(TNS)is reduced by 67.25%,and the number of violation paths is reduced by 170,which greatly reduces the difficulty of timing closure and shortens the design cycle.At the same time,the total design power also dropped to 78.88%.