Clock Tree Synthesis Based On EOC Phy

This paper is discussing how to achieve a more optimized implementation of the clock tree synthesis solution in the physical design of the EOC (Ethernet over Coax) physical layer chip BES7000. EOC is a technology of ethernet data transmission over coax. It is used in the high permeability and high bandwidth access to interactive television services in the future.Clock tree synthesis is a very important step in the high performance chip design. The rapid development of high-speed, low power consumption, high-performance of VLSI has put forward higher requirements for clock tree. The main objectives of clock tree synthesis is to minimize the clock skew and phase delay to provide maximum services for timing closure, meanwhile, to minimize power consumption, noise and coupling between connections of the clock network. A good clock tree design directly plays a crucial role in power, area, routing congestion and crosstalk of the entire design.This thesis did a deep research in areas of the most critical issues of clock tree synthesis. First of all, as chip designs continue to raise the highest working frequency and the design scale has been increased continually, accompanied by crosstalk coupling effects between the connections under deep sub-micron process, the requirement of timing closure is increasingly difficult to be met. And the clock tree synthesis is the most critical factor in timing closure. Secondly, to consider the test of mass production, in addition to the normal function mode other than test patterns is the design requirement as well, two models need to meet timing closure at the same time. It also makes clock tree synthesis present major challenges. Moreover, with access to deeper process nodes, the crosstalk effects in clock routing have a serious impact on the clock tree and timing closure in chip design.The design is completed on the EDA platform of Astro from Synopsys, based on BES7000 chip clock tree design. First it analyses the basic principles of clock tree, and plans for clock tree synthesis based on the flow of physical design, set clock port and clock tree synthesis parameters accordingly. Then it implements the basic clock tree synthesis based on the clock structure, analyses the result of timing closure, sums up the special problems BES7000 chips. And try a variety of strategies to find the most effective solution to solve these programs. In the stage of routing, according to the seriousness of crosstalk in 0.13μm technology, this figure out an improved routing method that can effectively solve the crosstalk affection to the clock tree.The results show that the clock tree synthesis program effectively solves problems coming with high frequency under deep sub-micron process, successfully satisfies the clock network demand of physical design of BES7000 chip, so as to meet the requirement of timing convergence at 250MHz frequency, and finally, the chip fabricated in TSMC0.13μm process successfully. The correct test results of the chip also verify the effectiveness of this clock tree synthesis program.