A Research Of Full-chip ESD Protection Based On Advanced Integrated Circuits

In recent years,with the rapid development of China's integrated circuit industry,many excellent semiconductor companies have emerged in succession.Many companies,research institutes and universities have also focused on the research of high-performance integrated circuits.The characteristics of high-performance integrated circuits,such as high working frequency and low power consumption,require the use of advanced process for manufacturing.In this context,the reliability of IC products is an important guarantee for its international competitiveness.In this paper,the research work of integrated circuit ESD full chip protection under advanced technology is carried out.In this paper,the basic concept of ESD is introduced firstly,and the loss of IC caused by ESD is also introduced.After that,the basic concept of ESD protection design is introduced,the guiding role of ESD protection design window in ESD Design is introduced,and ESD physical model and ESD test model are introduced.On this basis,the ESD principle of diode,BJT,MOS and SCR is explained.It shows that the transient characteristics of conventional SCR do not conform to the ESD Design window.The principle analysis of low trigger voltage SCR such as MLSCR and LVTSCR is introduced.In order to achieve voltage level compatibility,some I / O under advanced technology will work under high voltage,so ESD protection of high voltage I / O requires more effort.In order to achieve the whole-chip ESD protection,the performance of ESD device should be studied.In this paper,the research of diode,MOSFET,low trigger voltage SCR and Cascode device based on 28 nm CMOS technology are studied.Among them,the diode and MOS transistor have the characteristics of simple structure and strong process compatibility,which are the preferred devices for the whole-chip ESD protection.The research shows that the diode has the highest ESD robustness per unit area;MOSFET as ESD protection device does not need to optimize the trigger voltage and maintenance voltage;MLSCR,LVTSCR and MVSCR have the characteristics of hysteresis and very small on-resistance.In this project,the ESD performance of Cascode is studied for the high-voltage overdriven circuit.Cascode structure can effectively avoid the hot carrier agglomeration caused by high voltage on the gate of conventional device,resulting in the device performance degradation.This paper introduces the whole chip ESD protection theory.Considering the R&D time,manufacturing cost and performance stability,the whole chip ESD protection scheme based on power rail with fast R&D cycle and strong device stability is adopted.Firstly,the module of the protected chip is abstractly decomposed,and the relationship between each module and each power rail is abstracted.The chip is mainly divided into digital I / O module,analog I / O module and kernel logic module.The purpose of ESD whole chip design is to produce ESD event between any pin of any module,which has corresponding ESD discharge path to protect it.Based on the design of ESD device,the whole chip protection of ESD is completed.The result of taped-out shows that the highvoltage pin does not meet the protection standard under ND ESD pulse.For this,a followup improvement plan is proposed,and the problem point is successfully located and the solution is proposed.