Investigation Of ESD Protection Devices For MOS Integrated Circuits

With rapid development of semiconductor manufacturing technology, the feature size ofdevices in integrated circuits (ICs) decreases continuously, and the integration degree of ICchips increases stably. However, the companying reliability problems of devices and circuitsare also becoming more and more serious. Electrostatic discharge (ESD) has been one of themost important reliability issue in current semiconductor industry. According to the statistics,about half of the IC failure can be attributed to ESD. When the semiconductor processingtechnology steps into the nano era, a lot of traditional ESD protection devices and solutionscannot work as effectively as before. Furthermore, the increasing complexity of inner circuitsraises much higher requirements for I/O ESD protection. Therefore, improving or redesigningthe ESD protection structures based on the characteristics of modern process and newrequirements of inner circuits, are of great scientific and practical importance for providingeffective and reliable ESD protections.The focus of this thesis is studying the ESD protection devices for MOS ICs. Firstly, themethodology of on-chip ESD protection is introduced, and two different methods based onPAD and power supply line, respectively, are compared. Important ESD testing models,methods and instruments are also described. The detailed research work is consisted of thefollowing two parts.In the first part of this thesis, the working principles and improving designs ofconventional ESD protection units based on the diode, bipolar junction transistor and NMOSare studied systematically. The detailed research work includes the following parts. Firstly, inorder to analyze the ESD characterestics of the diode upon forward and the reverse bias, theI-V characterestics are investigated by transmission line pluse (TLP) testing, and the C-Vcharacterestics of DC-biased ESD diode are studied by simulation. The equivalent circuit ofthe ESD diode in a normally operated low noise amplifier (LNA) is proposed, which is thenverified by using a UHF LNA circuit. Secondly, the vertical NPN ESD protection structure ina5V0.6μm BiCMOS process is studied. To overcome the high trigger voltage ofconventional vertical NPN ESD self-triggered structure, a modified structure with aP+/N-Well diode is designed, in which the parasitic collector-base capacitance and the PNjunction capacitance are used as the capacitor coupler. The testing results indicate that theimproved structure has a significantly reduced trigger voltage, as well as an ESD protectionlevel passing4kV of human body model. The improved protection structure has beensuccessfully applied in a bipolar chip. Finaly, the ESD characteristics of gate-groundedNMOS (GGNMOS) are investigated in a0.18μm CMOS process. The effects of the devicesizes, layout parameters and manufacturing process on the ESD protection capability ofGGNMOS are analyzed. A DC macro-model of GGNMOS is also established.In the second part of this thesis, ESD protection devices based on silicon controlledrectifiers (SCRs) are studied in details. The protection principles of low trigger voltage SCRs,including NMOS low trigger voltage SCR (NLTVSCR), PMOS low trigger voltage SCR(PLTVSCR) and RC assisted low trigger voltage SCR, are analyzed. The corresponding devices are designed. Particularly, in order to reduce the high trigger voltage of conventionaldual-directional SCR (DDSCR), two modified structures, DDSCRs with embedded NMOSand PMOS (NMDDSCR and PMDDSCR, respectively) are proposed. Both the new structuresexhibit a lower trigger voltage, and have a holding voltage exceeding3.3V, making themsuitable for working in the1.8V and3.3V I/O protection applications reliably and immune tothe latch-up issue.