Research And Design Of ESD Protection Based On Advanced Integrated Circuit Process

With the development of the global semiconductor industry,the technology nodes of integrated circuit(IC)are shrinking continuously.At this time,the physical size of transistor is smaller and the chip size is larger,which renders semiconductor products more vulnerable to various electrostatic discharge(ESD)events,such as human body model(HBM),charged device model(CDM),and so on.As a result,it will deteriorate the semiconductor reliability and thus restrict the rapid itration of products seriously.Consequently,the ESD protection technique has become an indispensable research hotspot in semiconductor industry.This dissertation mainly involves the research of on-chip ESD protection engineering.Firstly,the challenges of ESD protection based on the advanced nanometer CMOS(Complementary Metal-Oxide-Semiconductor)process and three-dimensional FinFET process are discussed.Secondly,several advanced ESD protection applications are studied in depth,including the ESD protection of low-voltage circuit,high robustness circuit and bidirectional IC ports.The main work and innovation points of this dissertation are summarized as follows:(1)The protection of HBM and CDM events in advanced low-voltage processes is difficult,requiring ESD protection devices to have fast turn-on speed,low transient overshoot voltage,appropriate quasi-static triggering characteristics and superior clamping capability.In order to solve the above problems,two improved DTSCRs(Diode-Triggered Silicon-Controlled Rectifier)are proposed.By embedding the composite transistors(Sziklai pair and Darlington pair)with high current gain into the DTSCR device,the turn-on speed of the parasitic transistors and the establishment speed of current positive feedback in the SCR path can be improved greatly,thus reducing the turn-on time to picosecond level and obtaining more controllable quasi-static triggering characteristics.Secondly,in order to further optimize the transient overshoot voltage and clamping capability of DCSCR(Direct-Connected SCR),an improved DCSCR is also proposed.By optimizing the parasitic resistance of the auxiliary trigger diode path and the main SCR path,the overshoot voltage of device can be reduced and the clamping capability can be improved significantly,thus achieving 80%improvement of the area efficiency for CDM protection.Compared with their counterparts,the three devices proposed above are more suitable for advanced HBM and CDM protection projects.(2)A series of optimization works are carried out for the advanced and robust ESD protection.Firstly,in order to improve the current discharge ability of GGNMOS(Gate-Grounded N-MOSFET),which is commonly used in CMOS process,an enhanced GGNMOS is proposed.By embedding robust SCR current paths in the N-type guard ring,this device can achieve 4 times and 8 times robustness improvement compared with two traditional GGNMOS structures.Secondly,in order to identify the problem of ESD robustness degradation caused by current nonuniformity quickly,a TLP(Transmission Line Pulse)test methodology is proposed.Compared with the traditional failure analysis methods,this methodology is more convenient and economical to verify the current uniformity of ESD devices.Finally,the abnormal failure phenomenon of ESD devices in advanced epitaxial technology is also discussed,and two layout optimization methods of WELL resistance are proposed.Compared with the method of adjusting the WELL resistance length,the method of WELL pickup segmentation is more efficient since it can optimize the ESD protection performance of device greatly under constant device area.(3)For some advanced bidirectional I/O ports,ESD protection devices are usually required to have low trigger voltage,dual-directional current conduction capacity and compact layout.In order to meet the above design requirements,a compact and self-isolated DDSCR(Dual-Directional SCR)is proposed,which can achieve a very compact layout in an N-WELL.Compared with the traditional DDSCR devices,this device can achieve the highest ESD protection area efficiency(8.81V/?m~2).In addition,considering the holding voltage requirement for high voltage applications,the proposed DDSCR can also achieve the highest quality factor(63.4V~2/?m~2).Secondly,in order to meet the demand of advanced I/O ports for low trigger voltage,a low-voltage DDSCR is proposed.This device can achieve effective ESD protection for 3.3V/5V I/O ports in the 65nm process by using the N+/P-ESD junction as auxiliary trigger module.Finally,in order to overcome the influence of current saturation effect on the ESD robustness and protection effectiveness of DDSCR devices,an improved DDSCR is proposed.This device can suppress the current saturation phenomenon effectively and thus improve ESD robustness by 16.5%.