Investigation Of On-chip ESD Protection For RF CMOS Integrated Circuits

Electrostatic discharge (ESD) protection should be carefully designed for integrated circuit (IC) products to mitigate ESD threaten from natural environment, since ESD has become a serious reliability problem. It becomes extremely a challenge to design ESD protection for Radio frequency (RF) circuits. The parasitic capacitors brought by additional ESD protection devices will degrade the performance of the core RF circuits. On one hand, ESD devices must be sufficiently large to sustain the requirement of conducting a very large current generated by the ESD event. On the other hand, these devices must be relatively small to minimize their parasitic capacitance and the integrity of RF functionality. There is a trade-off between these two specifications. At present, ESD protection strategy for RFIC has been a hotspot and key point in ESD protection fields. In this dissertation, the main focus is on designing ESD protection strategies optimizing the ESD robustness and parasitic capacitors and realizing in RF circuits.Firstly, fundamental physical theory of ESD devices are given, followed by ESD circuit design, full chip ESD protection strategy and finally the simulation results of RF circuits with ESD protection are shown to validate the effect of parasitic capacitor brought by ESD protection devices on the RF circuits. All devices and circuits presented in this thesis are taped out in Semiconductor Manufacture International Corporation (SMIC) 0.18μm standard CMOS process and measured by BARTH 4002 Transmission Line Pulsing (TLP) system 4002.Main achievement in this thesis is concluded as following:1. ESD protection devices are studied.①ESD protection devices design: design window for ESD protection is presented according to the failure mechanism of CMOS devices. The operation mode of most important ESD devices diode, MOSFET, silicon controlled rectifier (SCR) under ESD condition is analyzed, followed by the methods to improve ESD devices' robustness and adjust the correlative electrical parameters of TLP's I-V, such as trigger voltage, holding voltage and current, failure current, turn-on resistance, device area, latch-up problem, leakage current.②ESD devices layout optimization technique: layout guidelines for optimizing ESD current distribution have been studied to improve the robustness of ESD devices.2. Full chip ESD protection strategies are studied.①Power Clamp design: Novel modified and poly-silicon diode string is applied to suppress the Darlington effect and thus decrease the leakage current of traditional diode string, including diode trigger SCR. RC trigger SCR is studied to replace normally used RC trigger MOSFET.②ESD protection for RF IC I/Os: Normally used dual-diode protection strategy and four novel design base on SCR complimentary SCR, current distribution area modified strip-type SCR (MSCRStrip), island-type modified SCR (SCRIsland), waffle SCR (WaffleSCR) are studied for RF I/O ESD protection. FOM evaluating the RF behavior is derived and show that SCR's is 2 - 3 times of diode's.③ESD protection for SMIC RF IPs: ESD protection solutions for 2.4 GHz LNA and PLL are given.Innovations in this thesis are as following:1. To solve the high trigger voltage problem of SCR, novel ESD protection strategy using power clamp to trigger SCR placed at I/O has been proposed. These four novel design - complimentary SCR, current distribution area modified strip-type SCR (MSCRStrip), island-type modified SCR (SCRIsland) and waffle SCR (WaffleSCR) - are studied. Test results show that FOM of SCR is 2 - 3 times of that of traditional ESD solution for RFIC dual diodes.2. Leakage current of poly-silicon diode string (patent applied) decrease 80% than traditional bulk silicon diode string by suppressing the Darlington effect. This technique is used for power clamp ESD protection design.3. To achieve uniform current distribution between fingers of ESD devices, layout guidelines including metal routing for GGNMOS and dual-directional SCR, P+ pick for GGNMOS, waffle structure for SCR are proposed. Test results show that the robustness of ESD devices improved dramatically. Especially for waffle SCR (patent applied) - the 4-direction symmetrical MLSCR structures, which costs only 39 percent silicon area of 2-directional stripe symmetrical layout, can achieve even better ESD robustness.4. ESD protection strategies for LNA and PLL are proposed, which can provide widely adapted ESD protection solution RFIC for SMIC.