The Research Of Full Chip Esd Design And Simulation In Deep-micron Cmos Technology

The motive of this dissertation is developed the whole chip ESD protection design methodology and simulation flow from the circuit designer view. ESD protection devices, circuits and full chip ESD protection network were analyzed and compared in this dissertation. The research object is realized the full chip ESD verification and simulation, based on the existing EDA tools, the dissertation development a design methodology integrated in SOC design flow. Using device level simulation, the influence of layout parameters and floorplan of ESD protection device were tested and analyzed. The design rule of 0.13um CMOS process is presented in this dissertation. Based on the physical model proposed in this dissertation, circuit level compact model and transient macro model were realized. From the full chip view, the dissertation is focused on full chip ESD verification and the placement of power pins. The transient macro model and simulation methodology were successfully used in the ESD protection design of WLED driver chip and OTPROM chip, the ESD test results are proven the feasibility and validity of these models.The contribution of this dissertation is listed as follows:(1) Based on the existing EDA tools developed the new ESD design methodology, it combines the process, device and circuit simulation together. Using this new design methodology, the designer can predict the ESD level of the chip before run silicon. Using this new design methodology, the design cycle is shortened greatly and the design accuracy is improved significantly.(2) Based on the TLP transient characteristic of GGNMOS, This dissertation presented a new transient macro model of GGNMOS. The model can accurately simulate the transient response of GGNMOS at ESD event. The model is simpler, and the simulation time is shorter, so the model is suitable for full chip ESD simulation.(3) This dissertation summarized the ESD failures caused by poor layout and circuits in internal chip. Using the Calibre DRC and LVS tools, the dissertation presented the ESD check list to avoid these ESD design errors in next chip design. (4) For high pin count, multi-power domain SOC, this dissertation presented a new transient simulation methodology. This methodology can optimize the power pin placement plan in order to archive the best combination between ESD performance and the numbers of pin.