Research On The On-Chip And Off-chip ESD Protection Design For RFIC

With the rapid progress of the integrated circuits?ICs?fabrication process and the radio frequency?RF?technology,the size of RFICs decreases continuously and their processing speed keeps increasing.Meanwhile,the electrostatic discharge?ESD?protection requirements of these chips is becoming higher,bringing new chanllenges to the ESD protection design.The impact of ESD on RFICs ESD has attracted wide attention,and some solutions meeting the ESD protection requirements of RFICs have been proposed.However,due to the diversity of fabrication process and application fields,these solutions are difficult to be applied in the latest RFICs with the ESD protection characteristics such as low trigger voltage ESD,high turn-on speed and low capacitance.Therefore,based on the fundamental ESD protection devices and the ESD requirements of RFICs,this thesis presents the on-chip and off-chip RFIC ESD protection solutions,respectively.The ESD performance of the designed ESD protection solutions is tested and evaluated by the transmission line pulse test?TLP?system and the network vector analyzer,respectively.The internal working mechanisms of the experimental devices are analyzed by Sentaurus simulations.Firstly,the working characteristics,the ESD protection requirements and the ESD protection design window of the RFIC are described.The TLP testing method,as well as the simulation flows of Sentaurus,is introduced.The ESD protection principles of some fundamental ESD protection devices such as diode,bipolar junction transistor?BJT?,gate-grounded NMOS?GGNMOS?and silicon controlled rectifier?SCR?,are analyzed in detail.The internal physical mechanisms of these devices under the ESD pulse stress are studied by Sentaurus simulations.Secondly,based on the on-chip ESD protection requirements and working charatersitics of RFICs,a series of modifed devices,such as the cross-bridge SCR?MLSCR?,the low-voltage trigger SCR?LVTSCR?,the dual-directional SCR embedded PMOS,the RC-triggered dual-directional SCR embedded PMOS and the diode-triggered SCR embedded NMOS?NMOS-DTSCR?,are designed and fabricated.The Sentaurus simulations and TLP testing results show that both MLSCR and LVTSCR devices can lower the trigger voltage effectively,but their holding voltage is low and the snapback voltage margin is large.Comparing to these two devices,the dual-directional SCR embedded PMOS has smaller snapback voltage margin,but its leakage current keeps high due to the uncontrollability of gate voltage.By introducing the RC triggering circuit to fix the gate volatage,the RC-triggered dual-directional SCR embedded PMOS can keep the leakage current in the order of 10^-10 A,reduce the snapback voltage margin to 1.33 V,lower the turn-on time to12.60 ns,and exhibit good ESD robustness.The shortcoming of this deivce is that it cons?mes a large chip area.By introducing NMOS in the diode-triggered SCR,the novel NMOS-DTSCR device can be realized,which has small trigger voltage and the holding voltage,the snapback voltage margin is as low as 0.20 V,the turn-on resistance decreases from 2.84?to 2.36?,and the failure current increases from 1.85 A to 3.13 A.Furthermore,the device has small chip area and low parasitic capacitance.The detailed ESD protection charatersitics of these experimental devices can provide useful reference for the on-chip ESD protection design of RFICs.Finally,based on the ESD protection requirements and working charatersitics of off-chip RFICs,the modified transient voltage suppressor?TVS?device is designed and fabricated.TLP testing and 3D TCAD simulation results show that the improved TVS has the advantages such as a low trigger voltage of 2.20 V,a small parasitic capacitance of 302 fF and a quite high failure current of 3.80 A.In order to further increase the device's turn-on speed,the layout of the N+region in the Pwell of modified TVS is optimized,helping to increase the turn-on speed by about 17.8%.Additionally,the turn-on resistance of the device can decrease continuously by introducing the floating gate in the modified TVS.The operation mechanism of experimental devices stressed by the ESD pulse is analyzed by Sentaurus simulations,and their electrical reliability is confirmed.