Study Of The ESD Protection Device And Its Operating Mechanism

Electrostatic discharge (ESD) is a major cause of integrated circuit (IC) failures. Industry surveys indicate that nearly 40% of IC failures are associated with ESD/EOS (electrical overstress) phenomena. Therefore, the study and controlling of ESD are indispensable for achieving higher quality and reliability standards of IC chips. As technology continues to scale, ESD becomes more and more important and needs to be handled as a key problem in the IC chips' manufacturing and using.In this thesis, toward the ESD protection device, an detailed analysis of the electrical and thermal behavior of GGNMOS under ESD stress is described, and the transient response to the ESD stress with duration less than 100ns is given. Then the conducting process of the parasitic lateral NPN transistor (LNPN) after triggering, the variation in temperature during the discharge process, and the influence of the high current on the field and temperature distribution are investigated. The triggering condition of the second breakdown and the influence of the substrate doping concentration on discharge process are discussed.The research of this thesis is based on the device physical level of GGNMOS. The results are more accurate and reliable than which got from the circuit level. So they can be made as the important references of design protection device to withstand several thousand ESD voltages.