Design Of High Speed Folding And Interpolating Analog To Digital Converter

With the rapid development of wireless communication,high-speed analog-to-digital converters(ADCs)is required for higher speed conversion in many areas,such as high-speed signal process,radar,mobile communication and radio astronomy.The Folding and Interpolating(F&I)ADC is widely used in high-speed comminication sysyems because of its high sampling rate,moderate accuracy.Therefore,it is of great value and significance to study high-speed,high-accuracy and low power F&I ADC.This paper analyzes folding technology and interpolating technology of F&I ADC in detail.The system scheme of this design combines the 8-bit precision system index and the folding circuit scale and design difficulty.Finally,two parallel 3-bit coarse quantization channels and 5-bit fine quantization channels are adopted.Bootstrapped switch with high linearity is adopted.Because the on-resistance of switch is constant,the sampling accuracy is improved;The preamplifier array with average network is used to redistribute the output impedance,which reduces the system offset error.The Monte Carlo simulation shows that the optimized preamplifier offset error is 1.8mV;The folding module adopts multi-way and cascade folding structure.The cascading structure adopts a folding unit with a folding coefficient of 3 to realize a folding curve with a folding coefficient of 9,and the multi-fold structure segments the folding curve to solve the folding mapping curve.Its solve the problem that the linearity difference of the folding map curve near the inflection point,and improving the linearity of the whole folding module;The interpolation technique with the interpolation coefficient of 16 greatly reduces the scale of the folding unit,and the scale of the folding network is reduced to the original 1/16.The interpolation network in the interpolation technique adopts a new scheme,which improves the linear matching degree between the interpolation curve and the original curve,thereby correcting the interpolation error of the system.The cooperative coding of Coarse-fine quantization method is used to optimize the coarse channel structure and improve the conversion accuracy of the ADC.An high-speed F&I ADC is designed which based on TSMC 130nm CMOS process and the chip area reaches 1.84×1.62mm~2.When the sampling rate is 1.5 GHz and the input frequecy is64.45MHz,The post-simulation results show that the SNDR is 47.39dB,SFDR is 59.31dBc,ENOB is 7.58bits.When the sampling rate is 1.5 GHz and the input frequecy is 744MHz,The post-simulation results show that the SNDR is 43.57dB,SFDR is 46.76dBc,ENOB is 6.95bits,the power consumption is 189.1mW.