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Design And Research Of High Speed Low Power Folding-Interpolating ADC Based On CMOS Standard Process

Posted on:2014-06-18Degree:MasterType:Thesis
Country:ChinaCandidate:W WangFull Text:PDF
GTID:2308330464957757Subject:Integrated circuit engineering
Abstract/Summary:PDF Full Text Request
Nowadays,mobile digital equipment develop so fast.the design of high speed, small size,low power,high performance Analog-to-Digital Converter (ADC) is becoming the bottleneck of mixed-signal SOC design,it consumes a lot of manpower and time.This dissertation mainly study and design a high speed, low power and middle resolution ADC, which can be used widely in Gigabit Ethernet, hard drive, LCD driver, TV set-top boxes and other fields.Based on the design requirements, this study uses folding and interpolating structure as the research direction.Folding and interpolating structure has some advantages such as high speed,small size,low power,ease of digital advanced process compatible.Comparing the same resolution ratio flash ADC,the folding circuit cut the resolution into coarse quantization and fine quantization,which can reduce the number of comparator, and then reduce the complexity of the circuit and design difficulty,also can reduce the circuit area and power effectively.The interpolating circuit can reduce the input capacitance and DNL which generated by the signal paths drift.This whole circuit use fully differential structure,it can improve the ADC noise immunity and enlarges the input voltage effectively.At the same time using interpolation resistance and offset averaging increases nonlinear performance of ADC,and further reduces power consumption..A bit synchronization scheme is proposed to correct the error caused by the signal path mismatch of original refence voltage between the coarse and fine channels.Base on UMC (United Microelectronics Corporation) 0.18-μm 1P6M CMOS process, the dissertation present the design of 8-bits,500MS/s Folding and Interpolating ADC. Using HSPICE-D tool, When the frequency of the input signal is 11MHz, SFDR is 58.8dB,SNDR is 48.2dB, ENOB is 7.72, the power consumption is 92mW. When the input in the Nyquist frequency 249MHz, SFDR is 54.8dB,SNDR is 47.3dB, ENOB is 7.56, the power consumption is 97mW.
Keywords/Search Tags:ADC, Folding, Interpolating, Fully Differential, Bootstrap Switch, Offset Average, CMOS
PDF Full Text Request
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