Research And Design Of A 10-bit Ultra-High-Speed Folding-Interpolating ADC

With the rapid development of digital signal processing technology, the signal processing speed of high-performance digital oscilloscopes, wireless communication base station and software radio systems to a large extent is subject to the conversion rate of the Analog-to-Digital Converter (ADC). The research of rapid-conversion ADC which is able to detect weak signal in radio frequency,will be of great significance to enhance the ascension of the whole system,such as data processing speed and accuracy.Among the variety of high-speed ADC, Folded-Interpolated ADC has a fairly full-parallel ADC conversion speed. Simultaneously, compared to full-parallel ADC is concerned, among the Folded-Interpolated ADC, the number of comparators converters can be reduced and overall power consumption and chip area can be reduced in the use of folding techniques and interpolation technique. However, compared to the fully-parallel ADC, its accuracy can be further improved. Based on the above-mentioned advantages of the folded-Interpolated ADC in achieving high conversion speed and high precision etc, this thesis research was carried out at the architectural level of the folded- Interpolated ADC. First of all, in this thesis, the structural characteristics of the Folded-Interpolated ADC introduced, and combined with 8-bit resolution of traditional architecture, its working principle is analyzed. Then, on this basis, the key factors in the architecture level that affect the Folded-Interpolated ADC speed and accuracy are discussed. Research on the use of multi-stage cascade folding techniques to improve the accuracy of the converter and pipelining technology to improve the speed of a converter are applied. At last, based on the above technique, completed the overall architecture design of the ultra-high-speed 10-bit Folded-Interpolated ADC, and give out the key structural parameters and design points of the architecture. And use the Verilog-A modeling language of Cadence Spectre simulation platform to complete the key behavioral modules of FI-ADC. On this basis, the overall behavioral model of the FI-ADC is completed and the simulation is done.In the sampling clock frequency of 1GHz, and the frequency of the input sine wave signal of 498.29MHz,4096 samples from the output signal of the converter are extracted for the discrete Fourier analysis (DFT). DFT analysis results of the output signal of the overall architecture of Verilog-A behavioral model is displayed, the effective number of bits (ENOB) of the converter reaches 9.6bits. The results fully demonstrate the feasibility of the design of the 10-bit ultra-high-speed Folded-Interpolated ADC architecture, and demonstrate the important role of the use of these technologies for improving the speed and accuracy of the converter.