Research And Design Of A 10-bit High-Speed Folding-Interpolating A/D Converter Key Circuit

With the further development of digital signal processing technology, high speed A/D converter is very important for digital filter, wireless communication base station,software radio, and other electronic system. The folding and interpolating A/D converter is a good choice for high speed A/D converter and using folding and interpolation technology. Folding and interpolating A/D converter inherits the high performance parallel analog-to-digital converter, the number of comparators is reduced. Becoming a hot spot in the field of high speed and high precision A/D converter.This dissertation is based on the traditional 8bit folding and interpolating A/D converter and studied Reference voltage generating circuit, pre-amplifier, the folding circuit and interpolation circuit realization principle and the non -ideal factors, The bottleneck of the key circuits in the design of high speed and high precision is analyzed .On the basis of the above analysis, the paper researched and designed 10-bit,500MHz folding and interpolating analog-to-digital converter. In architecture, the six cascade pipeline structure is used to increase the pretreatment time and improve the sampling rate of the quantization path. The design of reference voltage generation circuit, pre-amplifier, folding circuit, interpolation circuit, average resistance network and comparator in the quantization path of A/D converter are studied. In the reference voltage generation circuit, the LDO structure is used to stabilize the reference voltage.In the design of pre-amplifier, the offset average network is used to reduce the offset voltage of the circuit. At the same time, the trans-conductance of the input tube is increased, and the gain error caused by the different output resistance is adjusted. In the design of the folded circuit, the two stage cascade amplifier and the pre-reset tube are used to reduce the frequency doubling effect. In the design of the interpolation circuit,the interpolation delay error is reduced by 3 times interpolation. At the same time, the interpolation phase error is reduced by using the equivalent resistance.Finally in the cadence environment, based on TSMC 0.18?m CMOS process, Spectre software is used to simulate the whole quantization path, Simulation results show: The 3dB bandwidth of the pre-amplifier is 2.76GHz, which meets the performance requirements, and the pre-amplifier array produces the expected 27 benchmark zero crossings. The 3dB bandwidth of the folded circuit is 2.42GHz, which satisfies the performance requirements of the folded circuit, and the output curve of each circuit can realize the function of zero crossing. In the sampling clock frequency of 500MHz,and the frequency of the input sine wave signal of 249.51MHz, the input full swing of sine signal of 800mV, the effective bit of the converter quantization path reaches 9.61bits.The results show that the design of the 10-bit, 500MHz folded interpolation A/D converter meet the design requirements.