A Study Of Performance And Interpolation Methods In Folding And Interpolating A/D Converter

The research and development of analog-digital converter with high speed, low power consumption and small proportion is very significant in the application fields of WLAN, communication system and radar. With the nice features in speed, resolution, power consumption and proportion, folding and interpolating analog-digital converter becomes a study hotspot in recent years.This research employs the folded interpolated structure to design a high-speed analog-digital converter with 1.8V power supply, 10bit resolution, 1V input range and 100MS/s sampling rate by the use of standard CMOS process. In the circle design, this thesis is about the analysis and design of the whole ADC structure analysis and functions and performance of sub-ADC modules. By the thought of improving the system performance, reducing the impact of noise to the signal and restraining maladjustment error, to optimize key modules significantly improves the system capability. A high-speed sampling hold circuit that is fully-differential circuit with discrete CMFB is located; a distributed T/H circuit is inserted at the front end of preamp preamplifier, folding amplifier and sub-ADC to effectively insulate noises; dummy units are applied on the sides of preamp preamplifier to reduce the boundary effect; resistance interpolation by circular averaging network is located on the output terminals of preamp preamplifier, folding amplifier and sub-ADC to urge interaction between the terminals and remove interpolation boundary effect by odd symmetry of signals, which ameliorates DNL and INL of the system; besides, mathematical model is created based on the error by resistance interpolation and deeply analyzed, and three methods, which are brought forward to remove errors, and circuit structure is suggested; in the thesis, three interpolating methods are compared by the circuit structure and system performance.This paper design a 10bit 100MS/s ADC adopts SMIC 0.18μm 1P6M process. The maximum DNL is 0.6LSB, the maximum INL is 1.8LSB. At 16MHz sampling frequency input, the SNDR is 48dB, ENOB7.8. The effective area of chip is 1.6×1.6mm2.