The Design Of High Speed Folding And Interpolating ADC

With the development of computer and communication technology, and thedigital information age has arrived, the method how to convert the analog signals inreal life to digital signal used in computers becomes the key of many electronicequipments, so the design of ADC research will be the hot spot.ADC should have low power consumption, small area, high resolution and thehigh speed to be used in many kinds of different application conditions. But inpractice, there are contradictions between power, area, resolution and speed, and theperformances of different structures of the ADC are different too. Folding andinterpolating structures could be a good optimization to achieve ADC, this waydecrease the contradiction between power consumption and other indicators. Thispaper adopts the folding structure of interpolation, the design has realized the8-bitresolution,200MS/s sampling frequency.This paper introduces and analyzes the principle and structure of folding andinterpolating ADC firstly, then the paper gave out the modules needed in folding andinterpolating structure, such as pre-amp circuit, sampling hold circuit, folding,interpolation circuit, comparator and digital coding and so on. These modules havebeen carried on the theoretical study and simulation. For each circuit module, thispaper has illustrated the various factors that affect its performance, and varioussolutions have been proposed. In order to ensure the system’s high performance, allof the circuit modules adopt the differential structure. The amplifier circuit adoptsthe average-resistance technology to eliminate the disorder output. Sampling holdcircuit adopts distributed structure to reduce the linear range of the input sign alrequirements and the difficulty of the circuit design. Folding circuit uses two-stagecascading circuit to reduce the mismatch error. Interpolation circuit uses a series ofequivalent resistance to reduce the delay. This design provides a new typehigh-speed comparator, that can detect small signal range, and keep high speed moreconversion. Digital encoding circuit is realized by using digital logic circuit toachieve the function.Design of ADC circuit in this paper is based on TSMC0.18μm CMOS process,design and simulation under the Cadence Spectre environment, and performance ofcircuit is assessed by Matlab. When the Sampling frequency of ADC is under200MHz, the highest SNDR is48.4dB; when the input signal frequency is97.5MHz,the SNDR is35dB. The ADC has completed the design goal.