Design Of An 8-bit 320-MS/s Cascaded Folding And Interpolating ADC

As represented by ultra-wideband (UWB) technology, wireless technologies are changing the traditional concept of life.More portable, more stable and faster are the main purposes.The analog-to-digital converter (ADC) used for baseband signal processing is one of the most important blocks in a UWB system. The requirements of high speed and medium resolution limit the types that can be adopted. Moreover, ADCs consuming great power are not suitable for system-on-chip (SoC) embedded design. At present, the international researches on such application background are rare.Based on this situation, this thesis presents an 8-bit 320MS/s cascaded folding and interpolating ADC. The ADC abandons the traditional single-stage folding and single-stage interpolating structure and uses cascaded stages to increase the gain to overcome offset. Pipelined sampling switch saves the additional power consumption for signal establishment. The averaging resistor array is placed between two folding stages while well-designed layout reduces the parasitic loads. Both methods reduce power waste to some extent. The optimization of sample-and-hold circuit relieves the high-speed sampling clock feedthrough and charge injection effect. The Buffer stage separates the output and substrate capacitor skillfully so as to improve the circuit linearity.The ADC is fabricated in 0.13-μm CMOS process and achieves an effective area of 0.63 mm2.Measurements on ADC static and dynamic performance are presented at 1.2-V and 1.4-V supply voltage respectively. When in 1.4-V supply and 1-MHz input, ADC achieves 43.4-dB signal-to-noise and distortion ratio (SNDR) and 53.3-dB spurious-free dynamic range (SFDR).In the case of Nyquist frequency, SNDR and SFDR are 42.1 dB and 49.5 dB.Differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.75/-0.68 LSB and +1.4/-2.4 LSB.At 250-MHz sampling rate, power dissipation is 34 mW and the figure of merit (FoM) is 1.14 pJ/convstep.