High Speed Folding-interpolating ADC Research

In order to exchange messages between analog and digital world, analog-to-digitaland digital-to-analog converters were invented as intermedia between mankindcognition and digital world. With the downscaling of technology driven into deepsub-micron, large scaled integration circuit has developed rapidly, where digital circuitsgain tens of million gates and analog circuits feature frequency of GHz. TheAnalog-to-Digital Converter(ADC) has gain great achievement. However, there’s abottleneck for the self-developed ADC in high-tech signal process application, whererestrains the development of national whole machine system.In order to propose solutions to the problems above, the paper presents an8-bit2GSPS ultra-high speed ADC based on0.35μm BiCMOS process. Based on thepresent achievements of high level ADC of the institute, the structure and algorithm of8-bit2GSPS folding-interpolating ADC are analyzed and studied, which include thefollowing content:1.The overall structure of the ADC is studied. It’s hard to realize2GSPS samplingrate based on0.35μm BiCMOS process. Interleaved sampling structure of twochannel sub-ADCs is employed to make the analog circuit’s converting rate drop to1GHz, which increases the feasibility of circuit realization. Each channel ADC usesfolding-interpolating structure.2. The structure of the folding-interpolating ADC is studied based on0.35μmBiCMOS process. High3bit coarse and low5bit precision quantization are proposedas overall design. The paper thoroughly presents the conversion from analog signalinput to digital binary code output.3.Based on the theoretical demonstration, the paper presents the realization of thefolding-interpolating circuit. According to BiCMOS process, a novel folding circuit ofgreatly simplified structure is designed to increase the conversion rate. 4. In order to achieve a high performance of the designed ADC, various errors,which potentially cause the degradation of the ADC performance, are thoroughlyanalyzed for digital calibration of the folding-interpolating circuit to eliminate offseterror, gain error and matching error.5. Based on the paper, the encapsulation modeling and test of over2GSPS ADCare studied to accomplish the project design and to prove the validity of the circuit.6. On condition of484MHz sine input and2GSPS sampling rate, the A/Dconverter features SFDR of52dB, SNR of45.84dB, ENOB of7.32and DNL≤±0.4LSB, INL≤±0.5LSB. Test results exceed the expectation.