Research And Design Of Analog-to-Digital Converter Applied To Image Sensor

As an important component of the vision system,image sensors are widely used in digital photography,security monitoring,car driving,and medical imaging,etc.Analog-to-Digital Converter(ADC)is an important interface between photoelectric signal and digital image,and its performance directly affects image quality.To achieve an excellent balance between fill factor,conversion speed,quantization accuracy,and area overhead,ADCs are usually employed the column-level readout schemes.Because single-slope(SS)ADCs are not easily restricted by column widths and have excellent area efficiency,they are widely used in high-resolution application such as,digital cameras.For successive appromimation Register(SAR)ADCs,their faster conversion speed can well cope with the severe challenges brought by high frame rate fields such as security monitoring and automotive electronics.With the development of digital image technology and the industrial revolution triggered by the Internet of Things,people's growing demand for high-quality images inevitably promote ADCs towards higher resolution.As the resolution of the ADCs increase,the conversion speed of SS ADCs decrease exponentially,while the area of the capacitor array in the SAR ADCs inceasre exponentially.It is difficult for traditional ADCs to satisfy the harsh performance specification.Even without considering the area and speed limitations(the quantizer itself has a high resolution),the effective number of bits(ENOB)of the ADC is hardly to increase,which is mainly limited by circuit noise.These designs are unable to meet the special needs of high signal-to-noise ratio in the medical imaging.Hence,aiming at different application areas,this dissertation makes a comprehensive study on three perspectives:improving the speed of SS ADC,reducing the area of SAR ADC,and optimizing the ADC noise.The main contributions of this dissertation are as follows:(1)This dissertation proposes a two-step 12 bits SS ADC with a constant input common mode.Through the whole conversion,the input common-mode voltages of the comparator and ramp generator are always maintained at a fixed value,eliminating the dynamic offsets caused by the the limited common-mode rejection ratio.The normal 12bits A/D conversion is divided into upper 5-bit coarse conversion and lower 8.5-bit fine conversion(with 1.5 bit redundancy),which achieves high linearity while ensuring a high conversion rate.With the merge of the sampling path and the conversion path in the SS ADC,the negative input of the comparator can be set to a fixed common-mode voltage.Then,the coarse and fine ramp generators exploit a current-mode R-2R digital-to-analog converter(DAC)and a variable feedback resistor string DAC,respectively.The output buffers in the ramp generators both use the inverting amplifier topology instead of the traditional unity gain follower,which ensures the fixed common-mode voltage.A bottom-up digital foreground calibration algorithm is applied to reduce the nonlinearity caused by parasitic capacitor,offset voltage,and resistor mismatch.This prototype is fabricated using a 130 nm CMOS process with a core area of 7.5×675?m~2.The 12 bits two-step SS ADC achieves an ENOB of 9.8 bits when operating at a sampling frequency of 100KS/s and an input signal frequency of 48.8 k Hz.The measured differential nonlinearity(DNL)is+0.83/-1 LSB and the integral nonlinearity(INL)is+4.78/-3.31LSB.(2)This dissertation proposes a 14 bits hybrid SAR ADC based on charge transfer technique.The overall structure adopts a 9 bits traditional binary-segmented capacitor DAC and a 5 bits charge-redistribution serial capacitor DAC,which reduces the total number of weighted capacitors from 16384 of the traditional 14-bit SAR ADC to 53,which greatly improves the area efficiency.By transferring the charge,which is preset in the serial DAC,to the segmented DAC,a smaller weight voltage can be achieved without additional weight capacitors.The serial DAC only contains two conversion capacitors.Due to the monotonic of the serial capacitor DAC,it is used as a reference block together with the low-part of the segmented DAC to express and correct the high-part of the segmented DAC.This prototype is fabricated using a 130 nm CMOS process with a core area of 15×1450?m~2.The 14-bit 200 KS/s hybrid SAR ADC achieves an ENOB of 11.65 bits and a spurious-free dynamic range(SFDR)of 89.14 d B when the input signal frequency is 97.6 k Hz.The measured DNL is+0.87/-0.99 LSB,INL is+5.76/-4.37 LSB,and the total power consumption is 57?W.(3)This paper dissertation a third-order noise shaping SAR ADC based on the hybrid error control(HEC)structure.With only one operational amplifier,the overall circuit simultaneously realizes the feedforward summation and feedback superposition between the conversion residue and the input signal,which greatly simplifies the design complexity.Based on 8 bits DAC,this third-order noise shaping SAR ADC achieves an ENOB of 13 bits.The cascaded integrator feed-forward(CIFF)structure forms a feed-forward branch,and mainly adopts a first-order passive infinite impulse response(IIR)filter composed of a single integrating capacitor.The Error Feedback(EF)structure constitutes a feedback loop,which mainly uses a residual amplifier and a second-order switched capacitor finite impulse response(FIR)filter.Combining the average filter with the LMS algorithm,the capacitor mismatch information is accurately extracted from the output results without being affected by the quantization noise.It effectively solves the nonlinearity caused by the capacitor mismatch.This prototype is fabricated using a 130 nm CMOS process with a core area of 340×485?m~2.When operating at a sampling frequency of 2MS/s with an oversampling ratio of 8,this noise shaping SAR ADC achieves a signal-to-noise distortion ratio(SNDR)of 79.57 d B and a Schreier figure-of-Merit(Fo M)of 170.7 d B,and the total power consumption is 96?W.