Design Of 10bit 200KS/s Low Power SAR ADC

In low power applications such as environment monitoring and biomedical devices,analog-to-digital converter(ADC)is essential.In these systems,the input signals change slowly and the amplitudes are small and they are usually processed by ADCs with moderate resolution and sampling rate of 1-1000 KS/s.Among different ADC structures,due to its simple structure and excellent power efficiency,successive approximation register(SAR)analog-to-digital converters(ADCs)have been widely used in these low power applications.A low-voltage low-power 10-bit 200KS/s SAR ADC is proposed in this thesis.Firstly,this thesis describes the development status of low-power SAR ADC at home and abroad,and some low power design techniques commonly used in SAR ADC are summarized.On this basis,a low power switching scheme is proposed.Compared with the traditional scheme,the proposed switching scheme adopts split capacitor arrays and applies single-ended switching technique,achieving 99.76%energy saving and 75%less area occupation in the capacitor arrays.Besides,the sampling switch is optimized to reduce the impacts of non-ideal factors such as clock feedthrough and charge injection,ensuring the linearity of the sampling signal.Trading off the parameters such as noise,offset and power,the preamplifier-based comparator is used.In the aspect of digital control logic,synchronous clock is applied to simplify the time sequence design to ensure the reliability of circuit design.The design is fabricated in standard TSMC 40nm CMOS technology with its active die area of0.021mm~2.The post-simulation results show that the SAR ADC achieves 9.93ENOB at 200KS/s operating from a 0.6V supply.And the dynamic performances such as SFDR and SNDR are 67.8dB and 61.5dB,respectively.The total power consumption is 0.82?W,corresponding to a FoM of 4.20fJ/conversion-step.As a result,the SAR ADC satisfies the design requirements.