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Research On SAR ADC For Implantable Systems With Its Area And Power Optimization

Posted on:2014-11-02Degree:MasterType:Thesis
Country:ChinaCandidate:Y LiuFull Text:PDF
GTID:2268330425996847Subject:Electrical engineering
Abstract/Summary:PDF Full Text Request
As a chip embedded into the human body to process biomedical signals, the implantable system chip has strict requirements on its power and area optimization. On the other hand, since the Successive Approximation Register Analog to Digital Converter (SAR ADC) features low power and high precision and thus is suitable for these applications. This thesis adopted this type of ADC to construct implantable system chips and focused on its power and area optimization to meet the requirements of the high performance system.The thesis proposed an11bit,200KS/s SAR ADC circuit prototype and focused on design of some key modules including an integer-based split capacitor array, a time-domain comparator, a synchronous clock and successive approximation registers. The author improved the existing switching strategy and proposed a new switching strategy—the Terminating Capacitor Reused Method(TCRM) based on integer-based split capacitor array, which combines the advantages of split capacitor array and TCRM. This new strategy takes advantage of the terminating capacitor in the capacitor array to reduce the area and power consumption. Also it takes the design of split capacitor as integer multiples of the unit capacitor, which improves the mismatch of the capacitor as well as its nonlinearity. The new time-domain comparator with calibration module introduced in this work avoids static power consumption, of which the power consumption is reduced and the precision is enhanced. The successive approximation employs synchronous clock controlling to refrain from the problem of voltage mis-comparison and the time for each comparison or successive approximation is secured to keep them correct so as to improve the precision further.The proposed SAR ADC was designed in SMIC0.18um mixed signal process. The simulation results showed that the main expected functions were implemented. And an SNDR of61.5dB, an ENOB of9.9bits and a power dissipation of1.75μW were achieved, which means the optimization of power consumption and area was well realized. At the same time, its precision meets the demand of implantable medical chips to process the human biomedical signals.
Keywords/Search Tags:analog-to-digital converter, successive approximation register, switchingstrategy, time-domain comparator, synchronous clock
PDF Full Text Request
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