Research On Structure And Circuit Technology Of High-speed Successive Approximation Register Analog-to-Digital Converter

With the advancement of modern process technology,the development of communication technology has developed to a very high level in terms of interactive information capacity and signal transmission rate.In the upcoming 5G communication era,the information exchange rate and channel information carrying capacity will be further improved.The development trend of ultra-high-speed information interaction places higher performance requirements on all source devices(analog-to-digital converters,ADCs)for analog-to-digital conversion.The optical communications,5G will require conversion rates of the order of more than Giga Hz in future.To meet the needs of high-speed and ultra-high-speed performance,the successive approximation analog-to-digital converter(SAR ADC)stands out from the existing ADC system architectures because of its simple structure,low power consumption,high conversion rate,and gradually become mainstream high-speed system architecture design.This thesis takes the high-speed SAR ADC system structure as the research topic,and adopts the method of the single-channel SAR ADC structure to implement the high-speed SAR ADC architecture with two architectures respectively.First of all,a new type of 2bit/cycle SAR ADC is researched.Based on the traditional 2bit/cycle structure design,it integrates design resources,reduces the number of auxiliary capacitor DACs,reduces layout and overall power consumption,and optimizes system timing.The structure reduces the preset position operation and the number of quantization cycles in traditional design.At the same time,the design verification is performed with Vcm-based switching scheme,and analyzed the internal systemthe by analysis of the non-ideal factors of the system architecture.The module is optimized accordingly,reducing redundant time consumption and further improving the system's analog-to-digital conversion rate.Another research takes the alternate operation of two dynamic comparators as the core idea.By adding an auxiliary comparator into the traditional SAR ADC structure,to make those two dynamic comparators work alternately,which in turn makes the overall system in a continuous comparison state in order to reducing reset redundant time in traditional design.At the same time,for the internal module structure,a non-overlapping asynchronous clock generation circuit is independently designed,and the comparator control clock is optimized.In addition,the signal feedback loop is improved and a high-speed latch circuit is independently designed to further reduce redundant time consumption and realize a high-speed SAR ADC architecture.Both circuit architectures have been designed and verified under the SMIC 180 nm standard CMOS process,and completed related circuit system construction,layout drawing,simulation verification and other related work.And 2bit/cycle structure is verified under 180 nm process,with 1.8V power supply voltage,input frequency 49.85 MHz,and 100MS/s sampling rate.After the verification,the SNDR and SFDR are 57.21 d B and 66.4d B respectively.According to the post-simiulation data,under the condition of 10 ns period,the time margin is between 800 ps and 1ns,and the rate increase effect is obvious.The dual comparator architecture is also virifed under the 180 nm process.Under the same simulation parameters,the SFDR is 79.4d B,the SNDR is 58.5d B,and the ENOB is 9.44 bits.After the simulation,the overall conversion time is between 980 ps and 1.02 ns,and the conversion rate is close to 100MS/s.At the same time,an 8-bit design of 2bit/cycle structure was also verifed under the TSMC 28 nm standard CMOS process.With the 0.9V supply voltage,the conversion rate can reach 1.2GS/s,which achives a very good performance.