Design Of Fractional Frequency Dividers Applied To CMOS Frequency Synthesizer For 5G

The continuous development of modern wireless communication technology has created demands that a mobile terminal meet a variety of communication standards.Mobile terminals supporting multi-mode,multi-frequency band and multi-standard need continuous research and development.Frequency synthesizer is the core module of wireless transceiver.It has great effects on the overall transceiver performance,and with the fifth generation mobile communication technology is put on the agenda,it is necessary to further study and improve frequency synthesizer to make it meet new requirements.Fractional frequency divider is the key module of frequency synthesizer.In this thesis,the fractional frequency divider with CMOS technology is studied and designedThis thesis will introduce the components of frequency synthesizer and the working principle of each module.On this basis,some improvements on the fractional divider are proposed.The fractional frequency divider in this thesis mainly consists of three parts.The first part is the high speed frequency divider-by-2.It generates four orthogonal local oscillating signals.The second part is programmable frequency divider including a phase switching circuit,divide-by-4 and a divide-by-2/3 chain.The signal goes through frequency divider-by-4 and then generates eight signals.The phase difference between every two signals is 45 degrees.The phase switching circuit will select one of them according to the external signal to complete the phase switching function.The high speed divider-by-2/3 chain is made up of five divider-by-2/3.The frequency dividing ratio is extended by logic expansion circuit and it can meet the requirements of 50?500 frequency dividing ratio range.The third part is A-E modulator which is the key point in the research and a new structure of DDSM has been put forward The new structure can greatly increase the output sequence cycle and and the output sequence length is not affected by the initial state and external input value.So the fractional spur can be effectively suppressedThe fractional frequency divider is based on TSMC 0.18?m CMOS process.The chip area is 1.01×1.15mm2.The working frequency range of the fraction divider is 0.G?10.1GHz.The frequency division ratio ranges from 25 to 504 and the total current consumption is 9.7mA All measured results satisfy the design specification.