Design Of A CMOS Monolithic Σ-Δ Fractional Frequency Synthesizer

With the rapid development of IC (integrated circuits) fabrication processing and wireless communication technology, the implementation of a multi-standard, low-cost and fully integrated RF transceiver has become certainly the trend of development. The frequency synthesizer is a key building block in the RF transceiver. It is the determining factor of the overall performance of transceiver, and is also the biggest obstacle for its monolithic implementation. Due to theΣ-Δfractional-N frequency synthesizer completely overcomes the tradeoffs between loop bandwidth and channel spacing, and it can obtain a finer frequency resolution, lower phase noise and faster frequency switching, the more and more attentions have been put on it by the system designer recently.In this dissertation, the conventional techniques of frequency synthesis in wireless communication system are briefly reviewed, and the design methods of high performanceΣ-Δfractional-N frequency synthesizer are investigated. Several novel techniques are proposed to tackle the speed and integration bottlenecks of high-speed PLL.In order to overcome the disadvantage of traditional frequency divider, a new type of CMOS high-speed multi-modulus frequency divider is implemented, which is very suitable for the application of fractional-N frequency synthesizer. Comparing with the traditional frequency divider, it has the merits of high flexibility, high reusability and short design time. A capacitive scaler is proposed to reduce the chip area occupied by the large capacitors in the loop filter, thus an on-chip third-order passive filter is implemented. The key issue in the design of fractional-N frequency synthesizer is to eliminate the spurious tones come from fractional division. For this reason, the noise shaping effect of differentΣ-Δmodulators is analyzed, and a 3-bit third-orderΣ-Δmodulation technique as a spur reduction method to enhance the in-band noise and spur performance of synthesizer is proposed. Furthermore, the phase noise theory of LC VCO (voltage controlled oscillator) is thoroughly discussed, and the design techniques of spiral inductor and varactor are presented. Based on the analyzing and summarizing of the methods of improving their Q factor, a CMOS differential low phase noise LC-VCO is designed.